Alternatives and similar repositories for Pong

Users that are interested in Pong are comparing it to the libraries listed below

• zebmehring / Processor-Cache
  A Verilog implementation of a processor cache.
  ☆34Updated 8 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆95Updated 3 years ago
• kooltzh / xilinx-coe-generator
  Python script for generating Xilinx .coe files for RAM initializing
  ☆18Updated 7 years ago
• BrianHGinc / BrianHG-DDR3-Controller
  DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…
  ☆85Updated last year
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆44Updated 3 weeks ago
• RoaLogic / ahb3lite_memory
  Multi-Technology RAM with AHB3Lite interface
  ☆25Updated last year
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆68Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆83Updated 5 years ago
• freecores / pci
  PCI bridge
  ☆20Updated 11 years ago
• WillGreen / timetoexplore
  Source code to accompany https://timetoexplore.net
  ☆63Updated 5 years ago
• Wissance / QuickSPI
  Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface
  ☆21Updated 8 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆169Updated 4 years ago
• spider-tronix / VLSI
  RISC V core implementation using Verilog.
  ☆28Updated 4 years ago
• ChrisPVille / mig_example
  Example using DDR2 memory and MIG IP on the Nexys 4 DDR / Nexys A7 FPGA Trainer
  ☆36Updated 3 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆56Updated 5 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆125Updated 5 years ago
• RoaLogic / apb4_gpio
  General Purpose IO with APB4 interface
  ☆14Updated last year
• ATaylorCEngFIET / Mastering-MicroBlaze
  Slides and lab instructions for the mastering MicroBlaze session
  ☆36Updated 3 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆118Updated 2 years ago
• open-design / riscv-soc-cores
  ☆41Updated 4 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆69Updated 4 years ago
• geraked / verilog-rle
  Verilog Implementation of Run Length Encoding for RGB Image Compression
  ☆26Updated 4 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆61Updated 3 years ago
• someone755 / ddr3-controller
  A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
  ☆78Updated 3 years ago
• louisliuwei / FPGA-Design-Flow-using-Vivado
  This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
  ☆41Updated 6 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆123Updated 2 years ago
• mitya1337 / Simple_I2C
  Simple implementation of I2C interface written on Verilog and SystemC
  ☆47Updated 8 years ago
• barbedo / verilog-book
  Exercises of the FPGA Prototyping By Verilog Examples book by Pong P. Chu
  ☆23Updated 7 years ago
• mczerski / SD-card-controller
  WISHBONE SD Card Controller IP Core
  ☆130Updated 3 years ago
• adibis / DDR2_Controller
  DDR2 memory controller written in Verilog
  ☆78Updated 13 years ago