westonb / OV7670-Verilog

Related projects: ⓘ

• gtaylormb / ultra96v2_imx219_to_displayport
  Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL
  ☆65Updated 2 years ago
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆57Updated 4 years ago
• AngeloJacobo / FPGA_OV7670_Camera_Interface
  Real-time streaming of OV7670 camera via VGA with a 640x480 resolution at 30fps
  ☆49Updated 2 years ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆52Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆80Updated 2 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆75Updated 5 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆55Updated last year
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆94Updated last year
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆72Updated last year
• joelagnel / i2c-master
  An i2c master controller implemented in Verilog
  ☆31Updated 7 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• dawsonjon / verilog-math
  Mathematical Functions in Verilog
  ☆82Updated 3 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆134Updated last year
• Digilent / Zybo-Z7-20-pcam-5c
  ☆53Updated 2 years ago
• alexforencich / verilog-wishbone
  Verilog wishbone components
  ☆106Updated 8 months ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆104Updated 4 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆48Updated 10 years ago
• jamieiles / uart
  Verilog UART
  ☆118Updated 11 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆28Updated 2 years ago
• VideoGPU / MIPI_CSI2_TX
  VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes
  ☆56Updated last year
• samy-maxvy / MAXVY_MIPI_I3C_Basic_Master_Controller_IP
  It is Gate level netlist of MAXVY's MIPI I3C Basic Master Controller IP along with APB interface support.
  ☆15Updated 4 years ago
• freecores / video_stream_scaler
  Video Stream Scaler
  ☆39Updated 10 years ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆117Updated 10 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆45Updated 8 years ago
• teekamkhandelwal / asynchronous_fifo
  Asynchronous fifo using verilog and testbench using system verilog. For asynchronous Fifo design in different module.
  ☆28Updated 3 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆81Updated 4 months ago
• filipamator / adpll
  All digital PLL
  ☆24Updated 6 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆87Updated 6 years ago
• xupgit / Zynq-Design-using-Vivado
  This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.
  ☆76Updated last year