freecores / jpegencodeLinks
JPEG Encoder Verilog
☆78Updated 2 years ago
Alternatives and similar repositories for jpegencode
Users that are interested in jpegencode are comparing it to the libraries listed below
Sorting:
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆142Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- round robin arbiter☆75Updated 11 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- DDR2 memory controller written in Verilog☆78Updated 13 years ago
- AXI4 and AXI4-Lite interface definitions☆96Updated 5 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆157Updated 7 months ago
- AHB DMA 32 / 64 bits☆56Updated 11 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆138Updated last year
- H264视频解码verilog实现☆83Updated 8 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- AXI DMA 32 / 64 bits☆121Updated 11 years ago
- ☆79Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆107Updated 4 years ago
- ☆64Updated 3 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆45Updated 2 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆41Updated 3 years ago
- PCIE 5.0 Graduation project (Verification Team)☆80Updated last year
- ☆38Updated 10 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- Verilog SPI master and slave☆60Updated 9 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆87Updated 2 years ago
- A SATA host (HBA) core based on Xilinx FPGA with GTH to read/write hard disk. 一个基于Xilinx FPGA中的GTH的SATA host控制器,用来读写硬盘。☆117Updated 2 years ago
- Verilog digital signal processing components☆157Updated 2 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆33Updated 3 years ago