freecores / jpegencode
JPEG Encoder Verilog
☆74Updated 2 years ago
Alternatives and similar repositories for jpegencode:
Users that are interested in jpegencode are comparing it to the libraries listed below
- SDRAM controller with AXI4 interface☆89Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆63Updated 4 years ago
- AXI DMA 32 / 64 bits☆109Updated 10 years ago
- DDR2 memory controller written in Verilog☆74Updated 13 years ago
- HW JPEG decoder wrapper with AXI-4 DMA☆34Updated 4 years ago
- IP operations in verilog (simulation and implementation on ice40)☆55Updated 5 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- AHB DMA 32 / 64 bits☆54Updated 10 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆114Updated last year
- H264视频解码verilog实现☆79Updated 7 years ago
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- Bitmap Processing Library & AXI-Stream Video Image VIP☆30Updated 2 years ago
- round robin arbiter☆71Updated 10 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 7 years ago
- ☆36Updated 9 years ago
- Generic FIFO implementation with optional FWFT☆56Updated 4 years ago
- Fully parametrizable combinatorial parallel LFSR/CRC module☆146Updated last month
- AXI Interconnect☆47Updated 3 years ago
- AMBA bus generator including AXI, AHB, and APB☆99Updated 3 years ago
- An FPGA-based MPEG2 encoder for video compression (1920x1080 120fps). 基于FPGA的MPEG2视频编码器,可实现视频压缩。☆121Updated last year
- A Framework for Design and Verification of Image Processing Applications using UVM☆93Updated 7 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆42Updated last year
- AHB3-Lite Interconnect☆86Updated 10 months ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆30Updated 6 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆36Updated 2 years ago
- ARM中通过APB总线连接的UART模块☆63Updated 5 years ago
- Interface Protocol in Verilog☆49Updated 5 years ago
- RTL Verilog library for various DSP modules☆85Updated 3 years ago
- ☆59Updated 9 years ago