Alternatives and similar repositories for FastRMT:

Users that are interested in FastRMT are comparing it to the libraries listed below

• multitenancy-project / menshen
  ☆45Updated 2 years ago
• vishal1303 / PIEO-Scheduler
  A Fast, Scalable and Programmable Packet Scheduler in Hardware
  ☆38Updated 5 years ago
• minmit / tonic
  A Programmable Hardware Architecture for Network Transport Logic
  ☆34Updated 3 years ago
• l-nic / chipyard
  An Agile Chisel-Based SoC Design Framework
  ☆26Updated 3 years ago
• NetSys / irn-vivado-hls
  IRN's packet processing logic synthesized using Xilinx Vivado HLS
  ☆22Updated 6 years ago
• programmable-scheduling / pifo-hardware
  ☆30Updated 9 years ago
• NetFPGA / NetFPGA-PLUS
  ☆51Updated 7 months ago
• acsl-technion / nica
  An infrastructure for inline acceleration of network applications
  ☆30Updated 3 years ago
• ucsdsysnet / Rosebud
  Framework for FPGA-accelerated Middlebox Development
  ☆43Updated 2 years ago
• esnet / esnet-smartnic-hw
  ESnet SmartNIC hardware design repository.
  ☆45Updated last week
• ETH-PLUS / Jingzhao
  ☆40Updated 3 months ago
• p4fpga / p4fpga
  P4-14/16 Bluespec Compiler
  ☆83Updated 7 years ago
• utnslab / RingleaderNIC
  ☆13Updated last year
• axbryd / FlowBlaze
  FlowBlaze: Stateful Packet Processing in Hardware
  ☆67Updated 2 years ago
• anirudhSK / drmt
  ☆14Updated 7 years ago
• jhypolite / DeepMatch
  DeepMatch: Practical Deep Packet Inspection in the Data Plane using Network Processors
  ☆15Updated 4 years ago
• jijinfanhua / IPSA-ipbm
  ☆12Updated 2 years ago
• tcp-acceleration-service / FlexTOE
  Flexible, high-performance TCP offload to SmartNICs using fine-grained parallelism
  ☆59Updated 2 years ago
• Xilinx / RecoNIC
  RecoNIC is a software/hardware shell used to enable network-attached processing within an RDMA-featured SmartNIC for scale-out computing.
  ☆115Updated last month
• spcl / pspin
  PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
  ☆101Updated last year
• nsg-ethz / O4
  Reducing P4 Language’s Voluminosity using Higher-Level Constructs
  ☆15Updated 2 years ago
• HKUST-SING / srnic-simulation-public
  ☆18Updated last year
• packet-transactions / banzai
  A machine model for line-rate programmable switches
  ☆24Updated 8 years ago
• RC4ML / BenchBF3
  Demystifying Datapath Accelerator Enhanced Off-path SmartNIC [ICNP24]
  ☆31Updated 2 months ago
• agsiddharth / CAL-DPDK-GEM5
  Modifications to GEM5 for running kernel bypass networking. (DPDK)
  ☆15Updated last year
• opensmartnic / panic_with_cocotb
  ☆13Updated last year
• netx-repo / AIFO
  ☆44Updated 3 years ago
• pcie-bench / pcie-model
  ☆60Updated last week
• ncsg-group / csRNA
  ☆13Updated 8 months ago
• RC4ML / FpgaNIC
  FpgaNIC is an FPGA-based Versatile 100Gb SmartNIC for GPUs [ATC 22]
  ☆125Updated last year