RushikeshJagdale / 16-bit-ALU-View external linksLinks
DEsign 16-bit ALU using Verilog
☆10Feb 13, 2016Updated 10 years ago
Alternatives and similar repositories for 16-bit-ALU-
Users that are interested in 16-bit-ALU- are comparing it to the libraries listed below
Sorting:
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆24Feb 19, 2025Updated 11 months ago
- Simple android app for sending and receiving SMS messages☆10Apr 8, 2015Updated 10 years ago
- Innervator: Hardware Acceleration for Neural Networks☆18Aug 3, 2024Updated last year
- MD5 in VHDL☆11Jan 4, 2017Updated 9 years ago
- Single-cycle MIPS processor in Verilog HDL.☆10May 1, 2020Updated 5 years ago
- Beti Elektronik - ddApp -10 FPGA Uygulamaları (Eğitim) Seti☆13Dec 31, 2024Updated last year
- Our project involves the design of an 8-bit microprocessor data-path including 8-byte dual port memory, ALU and barrel shifter using CMOS…☆14Jan 2, 2021Updated 5 years ago
- Lecture about FIR filter on an FPGA☆13May 15, 2024Updated last year
- 本库为《数据结构与算法》(林劼、刘震、陈端宾、戴波主编)中的算法全实现,在学习过程中发现无论是书还是ppt中都有不少错误或者不清晰之处,故自行全实现☆12Dec 26, 2019Updated 6 years ago
- A synthesizable, five-stage, pipelined 32-bit RISC-V processor (implements the RV32I base ISA)☆12Apr 18, 2024Updated last year
- 【跟山地人学Vue.js系列教程】全38集☆13Feb 27, 2019Updated 6 years ago
- A simple count-town timer identical to android.os.CountDownTimer but with simplified usage and additional functionality to pause,resume a…☆14Feb 4, 2020Updated 6 years ago
- A retro-like car racing game made with python and tkinter.☆16Apr 15, 2023Updated 2 years ago
- Gathering frequently asked questions regarding Rice MCS 2021 Fall.☆11Aug 3, 2023Updated 2 years ago
- fpga verilog risc-v rv32i cpu☆14Apr 18, 2023Updated 2 years ago
- Demonstrates how to typeset urdu (both prose and poetry) in LaTeX☆12Sep 9, 2018Updated 7 years ago
- Design of 6T, 8T and 10T SRAM Cells with Static Noise Margin Analysis☆18Dec 9, 2022Updated 3 years ago
- HLS & hls4ml Tutorial☆15Aug 5, 2020Updated 5 years ago
- All Digital Phase-Locked Loop (ADPLL)☆26Jan 16, 2024Updated 2 years ago
- Your ultimate destination for Competitive Coding this Hacktoberfest21☆18Oct 31, 2021Updated 4 years ago
- Projects from Brno University of Technology☆12Jun 27, 2024Updated last year
- PID controller on an FPGA with custom RS232 addressing protocol.☆25Sep 7, 2021Updated 4 years ago
- Android application to turn off the music (and more) at the end of a countdown☆19Nov 4, 2021Updated 4 years ago
- mostly code assignments/reviews/practice on this Berkeley CS61B 2018 Spring course☆21Jun 24, 2021Updated 4 years ago
- Homework assignments for CIS 4710/5710☆30Updated this week
- 《机器学习实战》基于python3.6的代码实现☆20Feb 9, 2018Updated 8 years ago
- This hacktober fest, the only stop you’ll need to make for ML, Web Dev and App Dev - see you there!☆22Nov 10, 2021Updated 4 years ago
- Python Windows Wifi☆22May 13, 2024Updated last year
- few python scripts to clone all IP cores from opencores.org☆26Jan 8, 2024Updated 2 years ago
- ☆20Aug 27, 2022Updated 3 years ago
- A 16-bit Reduced Instruction Set Computing(RISC) processor capable of fetching and executing a set of 16-bit machine instructions.☆20Apr 4, 2024Updated last year
- Simple Alarm Clock Android app implemented with MVVM, Room, ViewModel and View Binding.☆28May 29, 2022Updated 3 years ago
- Implementation of RISC-V RV32I☆28Aug 30, 2022Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆26Jul 23, 2023Updated 2 years ago
- This repository is made to record the experiences and things learned by the mentees of the Cloudyman Mentorship Program☆36Oct 2, 2021Updated 4 years ago
- 안드로이드 키보드 샘플입니다.☆28Jul 20, 2020Updated 5 years ago
- Pipelined RISC-V CPU☆26Jun 9, 2021Updated 4 years ago
- bluetooth low energy example (mvvm)☆23May 7, 2024Updated last year
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago