RushikeshJagdale / 16-bit-ALU-
DEsign 16-bit ALU using Verilog
☆9Updated 9 years ago
Alternatives and similar repositories for 16-bit-ALU-
Users that are interested in 16-bit-ALU- are comparing it to the libraries listed below
Sorting:
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆13Updated 4 months ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆169Updated 6 years ago
- ☆111Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆122Updated 4 years ago
- VIP for AXI Protocol☆134Updated 2 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆103Updated 4 months ago
- ☆9Updated 2 years ago
- Single Cycle RISC MIPS Processor☆32Updated 3 years ago
- Single Cycle MIPS Pipelined Processor using Verilog☆14Updated 3 years ago
- Reference examples and short projects using UVM Methodology☆267Updated 3 years ago
- This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…☆19Updated last year
- 数字IC秋招项目、手撕代码☆35Updated last year
- Awesome ASIC design verification☆295Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆192Updated 4 years ago
- A basic testbench made for educational purposes using SystemVerilog and the Universal Verification Methodology☆102Updated 11 years ago
- ☆42Updated 3 years ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- This repository contains the design files of RISC-V Single Cycle Core☆43Updated last year
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- This project discusses the design of an 8-bit asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) impl…☆159Updated 6 months ago
- AMBA bus lecture material☆434Updated 5 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆148Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆46Updated 10 months ago
- The journey of designing an ASIC (application specific integrated circuit) is long and involves a number of major steps – moving from a c…☆331Updated this week
- Source code repo for UVM Tutorial for Candy Lovers☆186Updated 8 years ago
- UVM examples and projects☆135Updated 6 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆59Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆76Updated last year