Xilinx / RFNoC-HLS-WINLAB
☆16Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for RFNoC-HLS-WINLAB
- ☆26Updated 7 years ago
- ☆27Updated 9 months ago
- DMA source and sink blocks for Xilinx Zynq FPGAs☆22Updated 4 years ago
- A collection of RFSoC introductory notebooks for PYNQ.☆19Updated 3 years ago
- A High-Throughput Oversampled Polyphase Filter Bank Using Vivado HLS and PYNQ on a RFSoC☆24Updated 2 months ago
- MATLAB toolbox for ADI transceiver products☆57Updated this week
- OFDM implemented in MATLAB for USRP radios with MAC Layer☆42Updated 10 years ago
- DVB-S2 LDPC Decoder☆25Updated 10 years ago
- An RFSoC Frequency Planner developed using Python.☆20Updated last year
- IEEE 802.11ah transceiver☆23Updated 6 years ago
- RFSoC2x2 board repo for PYNQ☆17Updated 2 years ago
- PYNQ example of an OFDM Transmitter and Receiver on RFSoC.☆44Updated last year
- RFNoC out-of-tree module for a channelizer☆15Updated 6 years ago
- Dual-Mode PSK Transceiver on SDR With FPGA☆21Updated last month
- PYNQ example of using the RFSoC as a QPSK transceiver.☆91Updated last year
- This is a MATLAB SDR implementation of a LoRa receiver: demodulation and decoding☆24Updated 7 years ago
- Python productivity for RFSoC platforms☆57Updated 6 months ago
- Demonstration of Automatic Gain Control with PYNQ☆11Updated 2 years ago
- HDL code for a complex multiplier with AXI stream interface☆16Updated last year
- pynq framework for antsdr☆33Updated 5 months ago
- 64QAM Wireless communication on ADALM-PLUTO (a SDR active learning module), written in MATLAB, based on some APIs and existing functions.☆14Updated last year
- Orthogonal Frequency Division Multiplexing pipeline☆27Updated 6 years ago
- HDL code for a complex multiplier with AXI stream Interface☆13Updated last year
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆49Updated 2 weeks ago
- ☆68Updated last year
- Verilog library of EPC Gen-2 RFID Tag Baseband Processor for IC and FPGA designers☆29Updated 2 years ago
- DVB-S2 SDR Transceiver powerded by AFF3CT & StreamPU.☆24Updated 2 weeks ago
- RFSoC Spectrum Analyser Module on PYNQ.☆69Updated 4 months ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆36Updated 5 years ago
- Code for paper entitled "Low Cost FPGA based Implementation of a DRFM System"☆22Updated 2 years ago