anishagartia / Cache-Design
Implementation of Cache Simulator with Level 1, Level 2 and Victim Cache.
☆13Updated 8 years ago
Alternatives and similar repositories for Cache-Design:
Users that are interested in Cache-Design are comparing it to the libraries listed below
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆13Updated 11 months ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆10Updated 10 months ago
- Design and UVM-TB of RISC -V Microprocessor☆14Updated 7 months ago
- A Verilog implementation of a processor cache.☆24Updated 7 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆30Updated last year
- DUTH RISC-V Superscalar Microprocessor☆29Updated 3 months ago
- APB Logic☆13Updated last month
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆22Updated 2 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- SRAM☆21Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆25Updated 4 months ago
- Skid Buffer and Pipeline Skid Buffer designed in Verilog/System Verilog.☆15Updated 5 months ago
- WISHBONE Interconnect☆11Updated 7 years ago
- ☆40Updated 5 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆27Updated last year
- A Python package for generating HDL wrappers and top modules for HDL sources☆30Updated this week
- ☆25Updated 4 years ago
- This repository documents my work on Advanced Physical Design Using OpenLANE/Sky130. The objective of this project was to implement an op…☆14Updated 3 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆49Updated this week
- This is the FreePDK45 V1.4 Process Development Kit for the 45 nm technology☆21Updated 3 years ago
- ☆12Updated 2 years ago
- A MIPS CPU with dual-issue, out-of-order, and 5-stage pipelines☆11Updated 5 years ago
- The memory model was leveraged from micron.☆22Updated 6 years ago
- MathLib DAC 2023 version☆12Updated last year
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆30Updated last month
- Characterizer☆21Updated 5 months ago
- Contains all labs for EECS 251B for spring 2022☆9Updated 2 years ago
- Engineering Program on RTL Design for FPGA Accelerator☆26Updated 4 years ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆13Updated 4 years ago