Anushar123 / vsdsram
SRAM
☆7Updated 4 years ago
Related projects: ⓘ
- Design of 4KB Static RAM 1.8V (access time <2.5ns) using OpenRAM and Sky130 node☆13Updated 3 years ago
- sram/rram/mram.. compiler☆26Updated last year
- ☆19Updated 2 years ago
- 9 track standard cells for GF180MCU provided by GlobalFoundries.☆16Updated last year
- Library of open source Process Design Kits (PDKs)☆21Updated this week
- SRAM☆19Updated 4 years ago
- Minimal SKY130 example with self-checking LVS, DRC, and PEX☆23Updated 3 years ago
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆38Updated 4 years ago
- A RRAM addon for the NCSU FreePDK 45nm☆18Updated 2 years ago
- Network on Chip for MPSoC☆24Updated this week
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆38Updated last year
- This repository presents the mixed signal design of a Counter Type/ Ramp Type ADC. The Digital part of the circuit i.e 4- bit counter is …☆9Updated 2 years ago
- ☆15Updated this week
- Open source process design kit for 28nm open process☆38Updated 4 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆24Updated 3 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆17Updated 2 years ago
- Source codes and calibration scripts for clock tree synthesis☆38Updated 4 years ago
- Verilog Modules and Python Scripts for Creating IP Core Build Directories☆29Updated 10 months ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆15Updated last year
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆56Updated 3 years ago
- Design of 1024*32 (4kB) SRAM with access time < 2.5ns using OpenRAM☆20Updated 4 years ago
- ☆21Updated 4 years ago
- Open Source PHY v2☆23Updated 4 months ago
- LIS Network-on-Chip Implementation☆28Updated 8 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆13Updated last year
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆4Updated last year
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆29Updated 3 years ago
- RISC-V Rocket Chip Strap-on-Booster with Fused Universal Neural Network (FuNN) eNNgine☆21Updated 2 years ago
- 7 track standard cells for GF180MCU provided by GlobalFoundries.☆22Updated last year
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆28Updated 6 months ago