Ni-ChiTing / IC_contest_cell_based_designLinks
☆14Updated 4 years ago
Alternatives and similar repositories for IC_contest_cell_based_design
Users that are interested in IC_contest_cell_based_design are comparing it to the libraries listed below
Sorting:
- 交通大學iclab 2023 fall☆33Updated 10 months ago
- IC Contest☆39Updated 2 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆21Updated last year
- IC-contest 2012~2024☆20Updated last year
- ☆19Updated 2 years ago
- Computer-Aided VLSI System Design☆21Updated 10 months ago
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆13Updated 2 years ago
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 7 years ago
- 紀錄一下自己寫過的所有Lab☆33Updated last year
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆42Updated 2 years ago
- ☆38Updated 2 years ago
- ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.☆18Updated 2 years ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆13Updated 8 years ago
- ☆10Updated last year
- ☆13Updated 3 years ago
- NYCU ICLAB 2025 spring codes & 心得☆15Updated 3 weeks ago
- Some useful documents of Synopsys☆82Updated 3 years ago
- 交大電子所-積體電路實驗設計-李鎮宜教授☆12Updated 11 months ago
- AXI DMA 32 / 64 bits☆120Updated 11 years ago
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆91Updated 4 months ago
- 3×3脉动阵列乘法器☆46Updated 5 years ago
- 32-bit 5-Stage Pipelined RISC V RV32I Core☆52Updated last year
- 数字IC秋招项目、手撕代码☆37Updated last year
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆129Updated 11 months ago
- VIP for AXI Protocol☆148Updated 3 years ago
- ☆28Updated 7 months ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- AXI总线连接器☆103Updated 5 years ago
- An AXI4 crossbar implementation in SystemVerilog☆170Updated last week
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆129Updated 7 years ago