Ni-ChiTing / IC_contest_cell_based_design
☆10Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for IC_contest_cell_based_design
- IC Contest☆24Updated last year
- NCTU 2018 Spring Integrated Circuit Design Laboratory☆24Updated 6 years ago
- 交通大學iclab 2023 fall☆14Updated last month
- ☆19Updated this week
- ☆28Updated last year
- 國立陽明交通大學 電子所 積體電路設計實驗 李鎮宜教授☆12Updated last year
- 超詳細 ICLAB 2024 Spring 修課心得 & 修課指南,含資源整理☆30Updated 3 weeks ago
- Spring 2023 NYCU (prev. NCTU) Integrated Circuit Design Laboratory (ICLab)☆88Updated 2 months ago
- This repo is "NTHU VLSI System Design and Implementation" course project.☆11Updated 7 years ago
- 数字IC秋招项目、手撕代码☆33Updated 7 months ago
- A 32-point pipelined Fast Fourier transform processor, using single path delay architecture, and based on radix2-DIF(decimation-in-freque…☆40Updated 5 years ago
- ☆14Updated last month
- Computer-Aided VLSI System Design☆16Updated 3 weeks ago
- Discussion Forum for High-Level Synthesis (HLS) Courses in Taiwan.☆46Updated last year
- ☆14Updated last year
- Final Project of Software_Hardware_Co-Design_24Spring. FPGA-based RISC-V+ Convolutional Acceleration Unit.☆11Updated 6 months ago
- 紀錄一下自己寫過的所有Lab☆20Updated 10 months ago
- 清華大學 | 積體電路設計實驗 (IC LAB) | 110上☆25Updated 2 years ago
- Integrated Circuit Design Contest (ICDC) - 大學院校積體電路設計競賽☆11Updated 2 years ago
- ☆25Updated last year
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆49Updated 2 years ago
- AXI总线连接器☆91Updated 4 years ago
- [NYCU 2021 Spring] Digital Circuits and Systems☆13Updated 9 months ago
- ☆54Updated 4 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆111Updated 3 years ago
- ☆18Updated 4 years ago
- SPI interface connect to APB BUS with Verilog HDL☆25Updated 3 years ago
- This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is…☆54Updated last year
- UVM and System Verilog Manuals☆36Updated 5 years ago