SubZer0811 / verilog_grapherLinks
Graph your gate-level verilog code as a directed graph!
☆18Updated 4 years ago
Alternatives and similar repositories for verilog_grapher
Users that are interested in verilog_grapher are comparing it to the libraries listed below
Sorting:
- Routing Visualization for Physical Design☆19Updated 6 years ago
- ☆19Updated last year
- Hardware Formal Verification☆16Updated 5 years ago
- CMake based hardware build system☆31Updated last week
- ☆10Updated 4 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- Wallace and Dadda tree multiplier generator in vhdl and verilog☆11Updated 9 months ago
- A tool to generate optimized hardware files for univariate functions.☆28Updated last year
- Pathfinder routing algorithm practice☆15Updated 8 years ago
- ASIC Design kit for Skywater 130 for use with mflowgen☆13Updated 2 years ago
- A tool for synthesizing Verilog programs☆103Updated last month
- Generator of arithmetic circuits (multipliers, adders) and approximate circuits☆35Updated 2 months ago
- Anatomy of a powerhouse: SystemVerilog TPU based on Google TPU v1☆18Updated 4 months ago
- Benchmarks for High-Level Synthesis☆10Updated 2 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆23Updated last year
- Tutorial for integrating PyMTL and Vivado HLS☆19Updated 9 years ago
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆18Updated 2 years ago
- Convert C files into Verilog☆19Updated 6 years ago
- Digital Standard Cells based SAR ADC☆14Updated 4 years ago
- C++ and Verilog to implement AES128☆22Updated 7 years ago
- A standalone structural (gate-level) verilog parser☆39Updated last month
- ☆13Updated 5 years ago
- Provides a packaged collection of open source EDA tools☆12Updated 6 years ago
- Integer Multiplier Generator for Verilog☆23Updated 3 months ago
- OpenDesign Flow Database☆16Updated 6 years ago
- Logic optimization and technology mapping tool.☆19Updated 2 years ago
- EDA Analytics Central☆16Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆67Updated 8 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 4 months ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago