Alternatives and similar repositories for tree-sitter-vhdl

Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below

• gmlarumbe / tree-sitter-systemverilog
  SystemVerilog tree-sitter grammar
  ☆42Updated 2 months ago
• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆70Updated 8 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆188Updated 3 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆370Updated last month
• VHDL-LS / rust_hdl
  A fast VHDL language server and analysis library written in Rust
  ☆447Updated 3 weeks ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆219Updated last year
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆102Updated 7 months ago
• dalance / svls
  SystemVerilog language server
  ☆554Updated this week
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆114Updated last year
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆458Updated last month
• imc-trading / svlangserver
  ☆127Updated last month
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆65Updated last year
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆230Updated last month
• rggen / rggen
  Code generation tool for control and status registers
  ☆435Updated this week
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆338Updated last week
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆238Updated 3 months ago
• chaseruskin / orbit
  Package manager and build system for VHDL, Verilog, and SystemVerilog
  ☆58Updated this week
• chipsalliance / Surelog
  SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST & UHDM APIs. Compil…
  ☆430Updated 3 months ago
• chipsalliance / sv-tests
  Test suite designed to check compliance with the SystemVerilog standard.
  ☆352Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆72Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆163Updated last month
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆181Updated last week
• kevinpt / symbolator
  HDL symbol generator
  ☆198Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆220Updated 9 months ago
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆103Updated last week
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆160Updated 2 weeks ago
• pieter3d / simview
  ☆88Updated 2 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆65Updated 11 months ago
• thecooldaniel / nvim-config-systemverilog
  A minimum configuration for Neovim targeting SystemVerilog that provides configuration for plugin management, a language server, tree-sit…
  ☆22Updated last year
• hudson-trading / slang-server
  A SystemVerilog language server based on the Slang library.
  ☆82Updated last week