Alternatives and similar repositories for tree-sitter-vhdl:

Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below

• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆57Updated last month
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆95Updated 2 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆90Updated last year
• imc-trading / svlangserver
  ☆104Updated 7 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆148Updated 3 weeks ago
• dalance / svlint
  SystemVerilog linter
  ☆326Updated this week
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆198Updated 7 months ago
• gmlarumbe / tree-sitter-systemverilog
  Rewrite of tree-sitter-verilog
  ☆16Updated last week
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆133Updated last year
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆142Updated 2 months ago
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆41Updated 10 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆205Updated 2 months ago
• dalance / svls
  SystemVerilog language server
  ☆483Updated this week
• VHDL-LS / rust_hdl
  ☆361Updated 3 weeks ago
• hdl / bazel_rules_hdl
  Hardware Description Language (Verilog, VHDL, Chisel, nMigen, etc) with open tools (Yosys, Verilator, OpenROAD, etc) rules for Bazel (htt…
  ☆124Updated this week
• ThePerfectComputer / FastWaveBackend
  A Rust VCD parser intended to be the backend of a Waveform Viewer(built using egui) that supports dynamically loaded rust plugins.
  ☆42Updated 2 weeks ago
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆418Updated 2 months ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆275Updated last month
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 6 months ago
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆111Updated last month
• jeremiah-c-leary / vhdl-style-guide
  Style guide enforcement for VHDL
  ☆195Updated this week
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆77Updated 2 years ago
• pieter3d / simview
  ☆76Updated 10 months ago
• Jacajack / hdl
  A proof-of-concept, Rust-inspired, declarative hardware description language optimized for RTL coding
  ☆18Updated last week
• ghdl / ghdl-cosim
  Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL
  ☆47Updated this week
• slaclab / ruckus
  FPGA and Digital ASIC Build System
  ☆71Updated this week
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆64Updated last year
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆18Updated this week
• vhdl-linter / vhdl-linter
  ☆28Updated 7 months ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆55Updated this week