jpt13653903 / tree-sitter-vhdlLinks
A VHDL parser for syntax highlighting.
☆21Updated last week
Alternatives and similar repositories for tree-sitter-vhdl
Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below
Sorting:
- VHDL Language Support for VSCode☆71Updated 9 months ago
- A fast VHDL language server and analysis library written in Rust☆453Updated last week
- Language server based on ghdl☆102Updated 8 months ago
- SystemVerilog tree-sitter grammar☆43Updated 3 months ago
- A SystemVerilog Language Server☆195Updated last month
- Style guide enforcement for VHDL☆230Updated last week
- Repurposing existing HDL tools to help writing better code☆222Updated last year
- SystemVerilog grammar for tree-sitter☆113Updated last year
- ☆129Updated 2 months ago
- SystemVerilog linter☆373Updated 2 months ago
- Package manager and build system for VHDL, Verilog, and SystemVerilog☆60Updated last week
- VHDL grammar for tree-sitter☆32Updated 2 years ago
- A command-line tool for displaying vcd waveforms.☆65Updated last year
- Simple parser for extracting VHDL documentation☆74Updated last year
- A SystemVerilog language server based on the Slang library.☆104Updated this week
- Control and status register code generator toolchain☆166Updated last month
- HDL symbol generator☆200Updated 2 years ago
- Documentation with code examples about interfacing VHDL with foreign languages and tools through GHDL☆51Updated last week
- Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)☆66Updated 11 months ago
- WAL enables programmable waveform analysis.☆163Updated 2 months ago
- SystemVerilog language server☆558Updated last week
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆243Updated 4 months ago
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆194Updated this week
- A dependency management tool for hardware projects.☆342Updated last week
- SystemVerilog parser library fully compliant with IEEE 1800-2017☆461Updated 2 months ago
- VUnit GitHub action☆19Updated 4 years ago
- Rust Test Bench - write HDL tests in Rust.☆24Updated 3 years ago
- A JSON library implemented in VHDL.☆81Updated last month
- A translation of the Xilinx XPM library to VHDL for simulation purposes☆60Updated 2 months ago
- Limited python / cocotb interface to Xilinx/AMD Vivado simulator.☆72Updated 3 months ago