Alternatives and similar repositories for tree-sitter-vhdl

Users that are interested in tree-sitter-vhdl are comparing it to the libraries listed below

• VHDL-LS / rust_hdl_vscode
  VHDL Language Support for VSCode
  ☆65Updated 2 months ago
• tree-sitter / tree-sitter-verilog
  SystemVerilog grammar for tree-sitter
  ☆99Updated 6 months ago
• ghdl / ghdl-language-server
  Language server based on ghdl
  ☆93Updated 3 weeks ago
• benbr8 / rstb
  Rust Test Bench - write HDL tests in Rust.
  ☆23Updated 2 years ago
• imc-trading / svlangserver
  ☆112Updated last year
• kevinmehall / rust-vcd
  Read and write VCD (Value Change Dump) files in Rust
  ☆43Updated last year
• dalance / svlint
  SystemVerilog linter
  ☆347Updated 2 months ago
• vivekmalneedi / veridian
  A SystemVerilog Language Server
  ☆172Updated 2 months ago
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆58Updated last year
• psurply / dwfv
  A simple digital waveform viewer with vi-like key bindings.
  ☆139Updated 3 months ago
• VHDL-LS / rust_hdl
  ☆405Updated 3 weeks ago
• suoto / hdl_checker
  Repurposing existing HDL tools to help writing better code
  ☆208Updated last year
• pieter3d / simview
  ☆79Updated last year
• alemuller / tree-sitter-vhdl
  VHDL grammar for tree-sitter
  ☆31Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• HDLUtils / hdlregression
  HDLRegression: Simple, efficient, Python3-based FPGA regression test runner. Streamline the verification workflow.
  ☆24Updated last month
• openXC7 / toolchain-nix
  Nix flake for openXC7
  ☆38Updated 2 months ago
• Paebbels / JSON-for-VHDL
  A JSON library implemented in VHDL.
  ☆79Updated 2 years ago
• suzizecat / slang-lsp-tools
  Tools based upon slang for language server purpose
  ☆15Updated this week
• kevinpt / hdlparse
  Simple parser for extracting VHDL documentation
  ☆71Updated 10 months ago
• fossi-foundation / wishbone
  Specification of the Wishbone SoC Interconnect Architecture
  ☆45Updated 3 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆304Updated 2 weeks ago
• MikePopoloski / pyslang
  Python bindings for slang, a library for compiling SystemVerilog
  ☆58Updated 4 months ago
• chipsalliance / UHDM
  Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …
  ☆219Updated 3 weeks ago
• olofk / ipyxact
  Python-based IP-XACT parser
  ☆132Updated 11 months ago
• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆168Updated last week
• dalance / sv-parser
  SystemVerilog parser library fully compliant with IEEE 1800-2017
  ☆439Updated 3 months ago
• SystemRDL / PeakRDL-regblock
  Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
  ☆66Updated this week
• ekiwi / wellen
  wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.
  ☆66Updated last month
• ics-jku / wal
  WAL enables programmable waveform analysis.
  ☆153Updated this week