aitomatic / semikongLinks
First Open-Source Industry-Specific Model for Semiconductors
☆393Updated 9 months ago
Alternatives and similar repositories for semikong
Users that are interested in semikong are comparing it to the libraries listed below
Sorting:
- ☆261Updated last year
- Verilog evaluation benchmark for large language model☆370Updated 6 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆250Updated last year
- Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit☆175Updated last year
- ☆197Updated last year
- ☆109Updated 11 months ago
- ☆97Updated last month
- ☆123Updated 2 weeks ago
- This repo awesome-AI4EDA contains the source for the webpage: https://ai4eda.github.io, which is a curated paper list of awesome AI for E…☆184Updated 7 months ago
- ☆158Updated 2 years ago
- An open-source benchmark for generating design RTL with natural language☆155Updated last year
- An open-source EDA infrastructure and tools from netlist to GDS☆481Updated last month
- This repository hosts the information of SPICEPilot: a training free LLM data-augmentation, new bench marking and future road-map.☆26Updated 8 months ago
- Papers on LLM4EDA from 2023 and 2024☆46Updated last year
- LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation☆29Updated last year
- RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects - IEEE LAD'24☆33Updated last year
- CircuitNet: An Open-Source Dataset for Machine Learning Applications in Electronic Design Automation (EDA)☆446Updated 6 months ago
- MAGE: A Multi-Agent Engine for Automated RTL Code Generation☆86Updated 9 months ago
- Datasets for EDA LLM research☆37Updated last year
- ChatEDA: A Large Language Model Powered Autonomous Agent for EDA (TCAD'24, NAACL'25)☆42Updated 8 months ago
- The implementation of AICircuit: A Multi-Level Dataset and Benchmark for AI-Driven Analog Integrated Circuit Design☆80Updated last year
- ☆38Updated 2 years ago
- ☆42Updated 10 months ago
- ☆277Updated 5 years ago
- [DATE 2025] haven: hallucination-mitigated llm for verilog code generation aligned with hdl engineers☆38Updated 7 months ago
- LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust☆37Updated last year
- ☆119Updated 2 months ago
- Opensource software/hardware platform to build edge AI solutions deployed on FPGA or custom ASIC hardware.☆287Updated this week
- PDK for GlobalFoundries' 180nm MCU bulk process technology (GF180MCU).☆463Updated 2 years ago
- ☆40Updated 2 years ago