hadipourh / CryptoHDL

Related projects ⓘ

Alternatives and complementary repositories for CryptoHDL

• IAIK / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated last month
• GMUCERG / LWC
  Development Package for the Hardware API for Lightweight Cryptography
  ☆15Updated last year
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆72Updated 3 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 7 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆15Updated 8 months ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆46Updated 4 years ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon v1.2
  ☆20Updated this week
• IFM-Ulm / ro-pr-fw
  Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
  ☆10Updated 4 years ago
• aneeshkandi14 / ascon-hw-public
  ☆17Updated 4 months ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆34Updated 3 years ago
• jens-na / VexRiscv-CCOPI
  Custom Coprocessor Interface for VexRiscv
  ☆10Updated 6 years ago
• ascon / ascon-hardware-sca
  NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks
  ☆14Updated last year
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆24Updated last year
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆43Updated last year
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆73Updated 7 months ago
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆18Updated 4 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆37Updated 7 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆43Updated this week
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆60Updated last year
• Secure-Embedded-Systems / Masked-AES-Implementation
  ☆21Updated 4 years ago
• mbgh / aes128-hdl
  A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
  ☆38Updated 10 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆12Updated this week
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆76Updated this week
• ucb-bar / sha3
  ☆76Updated 8 months ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆27Updated 9 months ago
• hplp / aes_chisel
  Implementation of the Advanced Encryption Standard in Chisel
  ☆20Updated 2 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆35Updated 4 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆55Updated 3 months ago