Alternatives and similar repositories for CryptoHDL

Users that are interested in CryptoHDL are comparing it to the libraries listed below

• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆24Updated last year
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆91Updated 4 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆43Updated this week
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆35Updated this week
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆23Updated 5 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• KULeuven-COSIC / NTRU_NTT_HW
  ☆25Updated 4 years ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 5 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆55Updated 5 years ago
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆36Updated last year
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆37Updated 4 years ago
• chipsalliance / caliptra-ss
  HW Design Collateral for Caliptra Subsystem, which comprises Caliptra RoT IP and additional manufacturer controls.
  ☆36Updated this week
• coruus / canright-aes-sboxes
  David Canright's tiny AES S-boxes
  ☆28Updated 11 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆67Updated 3 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆51Updated 9 years ago
• ucb-bar / sha3
  ☆82Updated last year
• GMUCERG / LWC
  Development Package for the Hardware API for Lightweight Cryptography
  ☆18Updated 9 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆23Updated last year
• mbgh / aes128-hdl
  A high-throughput VHDL and SystemVerilog implementation of AES-128 including scripts for a full front-end design process.
  ☆42Updated 11 years ago
• BLu85 / AES-GCM-128-192-256-bits
  Configurable AES-GCM IP (128, 192, 256 bits)
  ☆38Updated 5 months ago
• embecosm / ri5cy
  The PULP RI5CY core modified for Verilator modeling and as a GDB server.
  ☆26Updated 7 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆61Updated 2 weeks ago
• unihd-cag / openhmc
  openHMC - an open source Hybrid Memory Cube Controller
  ☆50Updated 9 years ago
• IamFlea / AdderCircuitGenerator
  This script generates and analyzes prefix tree adders.
  ☆39Updated 4 years ago
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆79Updated 5 years ago
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆138Updated 3 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆47Updated 6 years ago