Alternatives and similar repositories for CryptoHDL:

Users that are interested in CryptoHDL are comparing it to the libraries listed below

• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated 7 months ago
• hadipourh / AES-VHDL
  VHDL Implementation of AES Algorithm
  ☆78Updated 3 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆32Updated 8 years ago
• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆38Updated 5 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• pnvamshi / Hardware-Implementation-of-AES-Verilog
  Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog
  ☆39Updated 7 years ago
• jens-na / VexRiscv-CCOPI
  Custom Coprocessor Interface for VexRiscv
  ☆9Updated 6 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆18Updated 10 months ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon
  ☆22Updated this week
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• ishfaqahmed29 / SerDes
  Verilog RTL Design
  ☆34Updated 3 years ago
• secworks / sha3
  FIPS 202 compliant SHA-3 core in Verilog
  ☆19Updated 4 years ago
• ucb-bar / sha3
  ☆79Updated last year
• momalab / CoPHEE
  CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.
  ☆31Updated last year
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆49Updated 4 years ago
• ascon / ascon-hardware
  NIST LWC Hardware Reference Implementation of Ascon v1.2
  ☆26Updated last year
• zdszx / Modexpowering3
  a 2048 bit RSA verilog project basing on Montgomery , Karatsuba multiplier
  ☆22Updated 3 years ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆52Updated 2 years ago
• kgpai94 / ECC-Encryption-System
  This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…
  ☆31Updated 6 years ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆14Updated 7 years ago
• KULeuven-COSIC / COSO-TRNG
  Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.
  ☆13Updated 5 months ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆31Updated last month
• IamFlea / AdderCircuitGenerator
  This script generates and analyzes prefix tree adders.
  ☆37Updated 4 years ago
• ben-marshall / croyde-riscv
  A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.
  ☆44Updated 3 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆81Updated last year
• arm-university / SoC-design-and-prototyping-Research-Enablement-Kit
  SoC design & prototyping
  ☆12Updated 3 years ago
• Deepak42074 / Sky130-RTL-Design-And-Synthesis-Using-Verilog
  ☆12Updated 2 years ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆21Updated last week
• freecores / sha3
  SHA3 (KECCAK)
  ☆18Updated 10 years ago