Alternatives and similar repositories for memalloy:

Users that are interested in memalloy are comparing it to the libraries listed below

• NVlabs / litmustestgen
  Alloy models for automatic synthesis of memory model litmus test suites (from ASPLOS 2017)
  ☆16Updated last year
• Ekdohibs / PolyGen
  PolyGen is a code generator for the polyhedral model, written and proved in Coq.
  ☆10Updated 4 years ago
• daniellustig / riscv-memory-model
  A formalization of the RVWMO (RISC-V) memory model
  ☆32Updated 2 years ago
• GaloisInc / grift
  Galois RISC-V ISA Formal Tools
  ☆58Updated 3 weeks ago
• David-Durst / aetherling
  Create auto-scheduled data-parallel pipelines in hardware with user-friendly Python
  ☆12Updated 4 years ago
• fpgasystems / fpga-hyperloglog
  FPGA-based HyperLogLog Accelerator
  ☆12Updated 4 years ago
• vegaluisjose / reticle
  ☆40Updated 3 years ago
• gussmith23 / lakeroad
  FPGA synthesis tool powered by program synthesis
  ☆41Updated last week
• TeamVoss / VossII
  The source code to the Voss II Hardware Verification Suite
  ☆56Updated this week
• agurfinkel / btor2mlir
  BTOR2 MLIR project
  ☆25Updated last year
• cliffordwolf / bextdep
  Reference Hardware Implementations of Bit Extract/Deposit Instructions
  ☆24Updated 7 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• elevate-lang / elevate
  The implementation of the Elevate language
  ☆29Updated last month
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• David-Durst / embeddedHaskellAetherling
  ☆25Updated 2 years ago
• aqjune / mlir-tv
  A translation validation framework for MLIR
  ☆81Updated last month
• rsnikhil / Bluespec_BSV_Formal_Semantics
  Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document
  ☆18Updated 8 years ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆44Updated last year
• cucapra / latte21
  Languages, Tools, and Techniques for Accelerator Design
  ☆33Updated 3 years ago
• mit-plv / kami
  A Platform for High-Level Parametric Hardware Specification and its Modular Verification
  ☆152Updated 7 months ago
• uwplse / rake
  compiling DSLs to high-level hardware instructions
  ☆22Updated 2 years ago
• project-oak / silveroak
  Formal specification and verification of hardware, especially for security and privacy.
  ☆126Updated 2 years ago
• gokhankici / iodine
  Iodine: Verifying Constant-Time Execution of Hardware
  ☆12Updated 4 years ago
• CakeML / hardware
  Verilog development and verification project for HOL4
  ☆26Updated 5 months ago
• NVlabs / ptxmemorymodel
  ☆53Updated 5 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• mc-imperial / multicore-test-harness
  A multicore microprocessor test harness for measuring interference
  ☆14Updated 5 years ago
• upscale-project / generic-sqed-demo
  ☆13Updated 4 years ago
• PrincetonUniversity / ILAng
  A Modeling and Verification Platform for SoCs using ILAs
  ☆76Updated 9 months ago
• mgudemann / iimc
  ☆12Updated 7 years ago