Alternatives and similar repositories for Vitis-AI-Reference-Tutorials

Users that are interested in Vitis-AI-Reference-Tutorials are comparing it to the libraries listed below

• sumilao / Zynq-7000-DPU-TRD
  Zynq-7000 DPU TRD
  ☆46Updated 6 years ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆61Updated 5 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆152Updated last year
• JinChen-tw / pynqz2_dpu140
  This TRD is implement DPU v1.4.0 on PYNQ-Z2 board
  ☆46Updated 5 years ago
• GJigar / ZYNQ_CNN
  ☆19Updated 3 years ago
• FedericoSerafini / HLS-CNN
  High Level Synthesis of a trained Convolutional Neural Network for handwritten digit recongnition.
  ☆41Updated last year
• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆39Updated 4 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 6 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆156Updated 2 years ago
• andre1araujo / YOLO-on-PYNQ-Z2
  This repository contains all the necessary material to implement a YOLOv3 object detection algorithm on the PYNQ-Z2 FPGA. There is a step…
  ☆79Updated 6 months ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆20Updated 4 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆35Updated 3 years ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆53Updated 3 years ago
• eepro-bt / documents
  文档编写
  ☆13Updated 5 years ago
• Xilinx / DPU-PYNQ
  DPU on PYNQ
  ☆227Updated last month
• user-xleo / DNN-Accelerator
  A DNN Accelerator implemented with RTL.
  ☆67Updated 8 months ago
• FloyedShen / mnist_hls
  Lenet for MNIST handwritten digit recognition using Vivado hls tool
  ☆37Updated 5 years ago
• thedatabusdotio / fpga-ml-accelerator
  This repository hosts the code for an FPGA based accelerator for convolutional neural networks
  ☆160Updated last year
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆48Updated 5 years ago
• bunny965 / yolov5-fpga-hardware-acceleration
  网络训练、图像预处理以及部分hend功能是基于pc端实现的，只有主干网络部署在fpga上，片上资源无法支持整个网络所需资源，建议添加外部存储及DDR
  ☆122Updated 2 years ago
• luyixdu / ZYNQ_ov5640_hdmi_frame_difference
  帧差法运动目标检测，基于ZYNQ7020
  ☆73Updated 4 years ago
• Zero0Hero / yolo_e203_fpga
  Nuclei E203 with yolo accelerator based on xc7k325
  ☆17Updated last year
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆48Updated 5 years ago
• Futuresxy / General-CNN-Accelerator
  General CNN_Accelerator design.卷积神经网络加速器设计。在PYNQ-Z2 FPGA开发板上实现了卷积池化全连接层等硬件加速计算。
  ☆64Updated 6 months ago
• Xinyang-ZHANG / MNIST
  MNIST using tensorflow, c++ and fpga (zynq7010)
  ☆25Updated 2 years ago
• ac-optimus / Convolution-using-systolic-arrays
  ☆66Updated 6 years ago
• qiujiandong / srio-controller
  在FPGA上实现SRIO收发控制器
  ☆11Updated 2 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 4 years ago
• devindang / openip-hdl
  Open IP in Hardware Description Language.
  ☆26Updated 2 years ago
• huanggeli / yolov3tiny-ZYNQ7000
  a Real-time image recognition project with RTL accelerator and ZYNQ Architecture
  ☆66Updated last year