Tutorials on Vitis AI Created by LogicTronix!
☆35Jul 5, 2024Updated last year
Alternatives and similar repositories for Vitis-AI-Reference-Tutorials
Users that are interested in Vitis-AI-Reference-Tutorials are comparing it to the libraries listed below
Sorting:
- ☆15Jul 15, 2024Updated last year
- yolov5-acceleration-fpga☆11Jun 25, 2025Updated 8 months ago
- Nuclei E203 with yolo accelerator based on xc7k325☆19Jul 19, 2024Updated last year
- FPGA Technology Exchange Group相关文件管理☆68Jan 3, 2026Updated 2 months ago
- ☆56Apr 19, 2023Updated 2 years ago
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- Bitonic sorter (Batcher's sorting network) written in Verilog.☆37Oct 4, 2024Updated last year
- 通过SPI协议实现FPGA multiboot在线升级功能☆13May 17, 2018Updated 7 years ago
- HDL and C source for WAVE Zynq Ultrascale+ SoC☆19Nov 16, 2021Updated 4 years ago
- Simple demo showing how to use the ping pong FIFO☆16May 2, 2016Updated 9 years ago
- [ICTA'21] First Prize Winner of the 2021 DIGILENT Cup, China College Integrated Circuit Competition☆276Apr 1, 2024Updated last year
- The implementation of AD9371 on KC705☆20Jun 10, 2025Updated 9 months ago
- Kria Motor control library☆21Aug 18, 2025Updated 7 months ago
- Open Source SSD Controller. NVMe and Lightstor variants☆17May 21, 2014Updated 11 years ago
- USB capture IP☆25Jun 6, 2020Updated 5 years ago
- Zynq/FPGA实现CNN手写数字(0-9)识别☆38Dec 14, 2024Updated last year
- Simple and effective parallel CRC calculator written in synthesizable SystemVerilog☆15Apr 11, 2019Updated 6 years ago
- LeNet-5 use c achieve☆13Jan 10, 2020Updated 6 years ago
- Based on C89, 3 methods☆15Apr 11, 2023Updated 2 years ago
- ☆19Aug 30, 2020Updated 5 years ago
- ☆18Jul 12, 2024Updated last year
- A Fix-pointed Rudimentary CNN Convolution Accelerator☆16Oct 7, 2020Updated 5 years ago
- Kratos: An FPGA Benchmark for Unrolled Deep Neural Networks with Fine-Grained Sparsity and Mixed Precision☆12Jan 19, 2026Updated 2 months ago
- ☆10Nov 22, 2022Updated 3 years ago
- zynqmp_cam_isp_demo linux软件项目☆22Dec 18, 2022Updated 3 years ago
- Project work on Spatial modulation and Quadrature Spatial modulation☆11Apr 9, 2018Updated 7 years ago
- 本项目使用 Vivado 和 SDK 工程软件上完成系统设计和生成相关部署文件,并在 ARM+FPGA 完成项目部署,实现通过摄取图片并通过 ARM+FPGA 综合部署和加速识别算法,并通过显示驱动,在显示屏上显示摄像头原图和识别结果。☆10Aug 12, 2022Updated 3 years ago
- Groundhog - Serial ATA Host Bus Adapter☆23Jun 10, 2018Updated 7 years ago
- Official Repo for "Multi-objective Differentiable Neural Architecture Search"☆15Jul 12, 2024Updated last year
- ☆12Oct 8, 2021Updated 4 years ago
- The goal of this design is to use the PYNQ-Z2 development board to design a general convolution neural network accelerator. And through r…☆11Sep 30, 2020Updated 5 years ago
- MMC (and derivative standards) host controller☆25Sep 14, 2020Updated 5 years ago
- ☆13Jul 10, 2024Updated last year
- Emulators for the STM32F4☆20May 8, 2019Updated 6 years ago
- Alkali is a MLIR-based compiler infrastructure for SmartNICs. It allows developers to write target-independent programs, with the compile…☆28Sep 28, 2025Updated 5 months ago
- Open-Channel Open-Way Flash Controller☆22Sep 10, 2021Updated 4 years ago
- Sparse CNN Accelerator targeting Intel FPGA☆12Aug 26, 2021Updated 4 years ago
- FPGA digital camera controller and frame capture device in VHDL☆15Feb 11, 2013Updated 13 years ago