基于高云FPGA与AD9363/AD9361射频收发器，构建了一套灵活可重构的软件无线电（SDR）系统，通信核心代码纯Verilog实现。软硬件全开源，高速基带处理部署于FPGA，交互业务部署于Python上位机，通过千兆以太网交互，实现了QPSK等多种实时通信与动态参数配置 Based on the Gowin FPGA and AD9363/AD9361 RF transceiver, a flexible and reconfigurable Software Defined Radio (SDR) system has been built, with the communication core implemented entirely in Verilog.
☆59Apr 1, 2026Updated last week
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