A robust, open-source physical layer implementation for FPGA-to-FPGA communication over high-speed serial links of the Quantum Error Correction interface (QECi) PHY layer.
☆33Sep 3, 2026Updated this week
Alternatives and similar repositories for qeciphy
Users that are interested in qeciphy are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- pcie datalink layer implementation in verilog/systemverilog☆17May 22, 2026Updated 3 months ago
- FPGA, CuDNN/CUDA & C++ Hybrid infrastructure for ultra low-latency algorithmic trading. Implements market data parsing, order book manage…☆23Apr 24, 2026Updated 4 months ago
- 10G Low Latency Ethernet☆109Jul 15, 2023Updated 3 years ago
- fcapz: Open-source, vendor-agnostic full-featured FPGA debug cores. Embedded Logic analyzer, Embedded I/O and Embedded JTAG-AXI☆116Aug 30, 2026Updated last week
- ☆16Aug 7, 2026Updated last month
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- 360nosc0pe Yocto build environment☆13Aug 27, 2018Updated 8 years ago
- ☆25Jun 14, 2026Updated 2 months ago
- HackerRank test solutions for FPGA engineer interview at Optiver☆15Jun 7, 2020Updated 6 years ago
- Verilog-A model library for photonic devices and components used in electronics-photonics co-simulation☆19Feb 10, 2026Updated 6 months ago
- Finding the bacteria in rotting FPGA designs.☆14Dec 28, 2020Updated 5 years ago
- PCIe stack written in Amaranth.☆18Apr 27, 2026Updated 4 months ago
- ☆14Aug 25, 2019Updated 7 years ago
- SNES for MiSTer☆16Sep 5, 2025Updated last year
- IHP 130nm ASIC tapeout of a 2x2 bfloat16 matrix matrix multiplication with DFT infrastructure. Iteration on the previous accelerator tape…☆43Jul 10, 2026Updated last month
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- ☆11May 30, 2024Updated 2 years ago
- DDR3 controller for nMigen (WIP)☆14Dec 25, 2023Updated 2 years ago
- MEEP FPGA Shell project, currently supporting Alveos u280 and u55c☆17Mar 14, 2024Updated 2 years ago
- PYNQ demo as seen at FPL 2018☆22Nov 23, 2020Updated 5 years ago
- XtraMAC code repo (Accepted by ISCA2026)☆28May 6, 2026Updated 4 months ago
- "Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)☆20Sep 26, 2024Updated last year
- Ready-to-link, packaged Aurora IP on four QSFP28 lanes, providing 100Gb/s throughput, flow control and status monitoring☆18Aug 14, 2026Updated 3 weeks ago
- High speed C/C++ based behavioural VHDL/Verilog co-simulation memory model☆35Feb 2, 2026Updated 7 months ago
- VUnit GitHub action☆19May 23, 2021Updated 5 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- FPGA implementation of DSITx (single lane) used in conjunction with ipod nano 7th gen display☆22Feb 22, 2018Updated 8 years ago
- RTL for AXI over UCIe bridge.☆29Aug 31, 2026Updated last week
- Generate bitstream from FPGA assembly.☆28Aug 11, 2026Updated 3 weeks ago
- u[Dark]RISC -- "micro-darkrisc" -- an early 16-bit micro-RISC processor defined before DarkRISCV☆20Jul 25, 2023Updated 3 years ago
- DFVG: A Heterogeneous Architecture for Speculative Decoding with Draft-on-FPGA and Verify-on-GPU.☆28Nov 26, 2025Updated 9 months ago
- Extracts specified data from a VCD file into CSV form☆10Jan 10, 2020Updated 6 years ago
- Bitstream Fault Analysis Tool☆16Jul 17, 2023Updated 3 years ago
- GenStore is the first in-storage processing system designed for genome sequence analysis that greatly reduces both data movement and comp…☆15Apr 6, 2022Updated 4 years ago
- SD device emulator from ProjectVault☆21Sep 24, 2019Updated 6 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- TCP Offload Engine☆79Nov 18, 2017Updated 8 years ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Jun 26, 2026Updated 2 months ago
- Open Logic FPGA Standard Library☆1,009Updated this week
- ☆13Updated this week
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆70Jan 10, 2024Updated 2 years ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆82Aug 10, 2026Updated 3 weeks ago
- This is a small demo of how to transform a simple single-server RocksDB service written in Rust into a distributed version using OmniPaxo…☆16Feb 5, 2025Updated last year