casper-astro / casper-hardwareLinks
A repository of information and source files for toolflow-supported hardware
☆31Updated 3 years ago
Alternatives and similar repositories for casper-hardware
Users that are interested in casper-hardware are comparing it to the libraries listed below
Sorting:
- Projects published on controlpaths.com and hackster.io☆41Updated 3 years ago
- A basic Soft(Gate)ware Defined Radio architecture☆93Updated last year
- AMC module with Xilinx RF-SoC and two analog front-end mezzanines for SDR and quantum applications☆39Updated 2 years ago
- OscillatorIMP ecosystem for the digital characterization of ultrastable oscillators and Software Defined Radio (SDR) frontend processing☆57Updated last month
- RF electronics engineering ecosystem☆30Updated 3 years ago
- Basic loadout for SQRL Acorn CLE 215/215+ board. Blinks all LEDs, outputs square waves on all 12 GPIO outputs☆68Updated 3 years ago
- Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC☆109Updated 8 years ago
- An adapter board with pin headers for low-pin count (LPC) FPGA Mezzanine Cards (FMC).☆10Updated 4 years ago
- Small footprint and configurable JESD204B core☆45Updated 3 months ago
- ☆36Updated 11 months ago
- An RFSoC Frequency Planner developed using Python.☆30Updated 2 years ago
- ☆43Updated 2 years ago
- LiteX Accelerator Block for GNU Radio☆24Updated 3 years ago
- LiteX development baseboards arround the SQRL Acorn.☆68Updated 5 months ago
- ☆61Updated last month
- assorted library of utility cores for amaranth HDL☆96Updated 11 months ago
- An SDR for Raspberry Pi☆35Updated 5 years ago
- Open source AMD Xilinx Kria UltraScale+ SoM baseboard☆50Updated 7 months ago
- LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled☆64Updated 2 weeks ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆117Updated 4 years ago
- PYNQ example of using the RFSoC as a QPSK/BPSK radio transceiver.☆37Updated 2 years ago
- A fully-integrated FT8 protocol receiver on 130nm CMOS☆60Updated 2 years ago
- openEMS High-level layer☆19Updated 5 months ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- An 8-layer board in Kicad built upon Xilinx Zynq Chip. Includes sound output, HDMI, DDR3, and Arduino Uno style header for screen connect…☆65Updated 3 years ago
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆66Updated last month
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆31Updated 3 years ago
- ☆48Updated 4 years ago
- An Amateur Radio Transceiver IC (2.4 / 5 / 10 GHz)☆71Updated 3 years ago
- Software control for CASPER FPGAs☆19Updated last year