Alternatives and similar repositories for Axi4-lite

Users that are interested in Axi4-lite are comparing it to the libraries listed below

• shariethernet / RPHAX
  RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…
  ☆19Updated 2 years ago
• CEatBTU / FGPU
  FGPU is a soft GPU-like architecture for FPGAs. It is described in VHDL, fully customizable, and can be programmed using OpenCL.
  ☆57Updated 7 months ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• taneroksuz / fpu
  IEEE 754 single and double precision floating point library in systemverilog and vhdl
  ☆67Updated 7 months ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• ShaheerSajid / RISCV
  32-bit soft RISCV processor for FPGA applications
  ☆16Updated last year
• pulp-platform / hyperbus
  ☆26Updated last week
• k0nze / zedboard_axi4_master_burst_example
  Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)
  ☆44Updated 8 years ago
• aignacio / mpsoc_example
  ☆59Updated 3 years ago
• PXVI / ip_amba_ahb_ms_rtl_v
  RTL design for the AMBA AHB protocol.
  ☆8Updated this week
• klessydra / T13x
  An Extended Version of the T0x multithreaded cores, with a custom general purpose parametrized SIMD/MIMD vector coprocessor and support …
  ☆46Updated 11 months ago
• aignacio / nox
  RISC-V Nox core
  ☆66Updated 4 months ago
• esa-tu-darmstadt / tapasco-riscv
  RISC-V soft-core PEs for TaPaSCo
  ☆22Updated last year
• AlSaqr-platform / he-soc
  ☆31Updated last week
• RoaLogic / Hamming-ECC
  Hamming ECC Encoder and Decoder to protect memories
  ☆33Updated 5 months ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆110Updated 8 months ago
• damdoy / fpga_image_processing
  IP operations in verilog (simulation and implementation on ice40)
  ☆58Updated 5 years ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆63Updated 6 months ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆75Updated 2 years ago
• siorpaes / SimpleSoC
  Very simple Cortex-M1 SoC design based on ARM DesignStart
  ☆17Updated 3 years ago
• os-fpga / FOEDAG
  Framework Open EDA Gui
  ☆68Updated 7 months ago
• srimanthtenneti / SOC-Design-ARM-M0
  This is a repo containing ARM-Cortex-M0 based SOC designs implemented on the Nexus-4-DDR , Nexus-4 and the ARTY - A7 FPGA platforms.
  ☆11Updated last year
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆35Updated 7 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆66Updated 5 months ago
• taichi-ishitani / rggen
  This repository is no longer maintained. New repository is here(https://github.com/rggen/rggen).
  ☆17Updated 5 years ago
• mashahedurrahman / Security-Engine
  ☆12Updated last year
• yigitbektasgursoy / SDRAM_Verilog
  Verilog HDL implementation of SDRAM controller and SDRAM model
  ☆27Updated last year
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆32Updated 4 years ago
• ultraembedded / cortex_m0_wrapper
  Cortex-M0 DesignStart Wrapper
  ☆19Updated 5 years ago
• Digilent / Petalinux-Zybo-Z7-20
  ☆53Updated 2 years ago