This repository contains the implementation of AXI4-Lite interface protocol on system verilog for FPGA/ASIC communication. Modular codebase with example designs and testbench.
☆17May 4, 2024Updated last year
Alternatives and similar repositories for Axi4-lite
Users that are interested in Axi4-lite are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated 11 months ago
- Design and UVM Verification of an ALU☆11Jun 14, 2024Updated last year
- Verilog HDL code and Finite State Machine (FSM) for a simple ATM☆12Jul 26, 2020Updated 5 years ago
- Python script for generating Xilinx .coe files for RAM initializing☆18Jan 3, 2019Updated 7 years ago
- FPGA based, Real-time processing of audio, including voiceprint recognition, adaptive noise suppression, et al.☆15May 8, 2025Updated 10 months ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting with the flexibility to host WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Cloudways by DigitalOcean.
- Generate SystemVerilog/UVM block level testbench setup with python script☆11Oct 3, 2017Updated 8 years ago
- RTL Design and Verification☆18Jan 4, 2021Updated 5 years ago
- A project to perform the VLSI Physical Design Flow steps of partitioning, floorplan, placement and routing.☆13Jun 9, 2021Updated 4 years ago
- ☆12Mar 1, 2021Updated 5 years ago
- PC-side code for PacGoc, enterprise grand prize-winning work at PangoMirco Cup CICC 2024. [第八届集创赛紫光同创杯企业大奖获奖作品]☆18Oct 12, 2024Updated last year
- These books are pulled from # List of Free Learning Resources [ design space.☆18Nov 23, 2017Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click and start building anything your business needs.
- MOSIS MPW Test Data and SPICE Models Collections☆40Apr 2, 2020Updated 5 years ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆18Jul 7, 2021Updated 4 years ago
- Elgamal's over Elliptic Curves☆20Dec 22, 2018Updated 7 years ago
- A guide on how to package HDL code (VHDL or Verilog) for PYNQ environments☆11Aug 14, 2025Updated 7 months ago
- Workforce management tool for mobile teams☆15Sep 3, 2017Updated 8 years ago
- Quick Example how to generate an custom AXI4 IP with AXI4-Full interface (burst) for the Zynq (ZedBoard)☆45Jun 7, 2017Updated 8 years ago
- [CVPR 2024] Official implementation for "A&B BNN: Add&Bit-Operation-Only Hardware-Friendly Binary Neural Network"☆24Dec 5, 2025Updated 3 months ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现，基为2，有两个并行的蝶形单元☆19Sep 16, 2022Updated 3 years ago
- PYNQ bindings for C and C++ to avoid requiring Python or Vitis to execute hardware acceleration.☆30Feb 23, 2026Updated last month
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- A Verilog implementation of a processor cache.☆37Dec 29, 2017Updated 8 years ago
- An unofficial ASIO driver for the QuantAsylum QA403, QA402 and QA401 audio analyzers.☆14May 15, 2024Updated last year
- ☆42Dec 19, 2024Updated last year
- Implementation of markov chains in Cpp☆16Oct 23, 2019Updated 6 years ago
- AMD University Program HLS tutorial☆124Oct 28, 2024Updated last year
- Collection of kernel accelerators optimised for LLM execution☆28Feb 26, 2026Updated last month
- Alveo Versal Example Design☆61Jan 28, 2026Updated 2 months ago
- Sample UVM code for axi ram dut☆39Dec 14, 2021Updated 4 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆15Mar 2, 2022Updated 4 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Curated list of original content in European Portuguese (PT-PT)☆18Oct 24, 2024Updated last year
- PCI_Express总线经典书籍☆27May 13, 2022Updated 3 years ago
- ☆28Aug 19, 2025Updated 7 months ago
- Verilog HDL implementation of SDRAM controller and SDRAM model☆40Jun 19, 2024Updated last year
- ☆26Nov 3, 2020Updated 5 years ago
- Example project for the BRS-100-GW1NR9 FPGA development board.☆14Feb 14, 2026Updated last month
- Study notes and tutorial for xilinx hls☆20Jul 22, 2021Updated 4 years ago