DNA-and-Natural-Algorithms-Group / peppercornenumerator
domain-level nucleic acid reaction enumeration
☆10Updated last year
Related projects ⓘ
Alternatives and complementary repositories for peppercornenumerator
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆13Updated 3 weeks ago
- zGlue Chiplet Info Exchange Format (ZEF)☆10Updated 3 years ago
- Piperine compiles abstract CRNs into DNA sequences and estimates how much the generated DNA implementations may participate in undesired …☆21Updated 11 months ago
- moderngpu algorithms for C++ shaders☆16Updated 3 years ago
- ☆10Updated 5 years ago
- LLVM-Canon aims to transform LLVM modules into a canonical form by reordering and renaming instructions while preserving the same semanti…☆12Updated 6 months ago
- I ❤︎ FEM: A finite element method demo in Umka and tophat☆16Updated 2 months ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- ✔️Port of RISCOF to check the NEORV32 for RISC-V ISA compatibility.☆25Updated this week
- Main Repo for the OpenHW Group Software Task Group☆15Updated last week
- ABC: System for Sequential Logic Synthesis and Formal Verification☆27Updated 2 weeks ago
- ☆34Updated 7 months ago
- Quite OK image compression Verilog implementation☆15Updated 5 months ago
- Polyhedral Compilation tool for High Level Synthesis.☆10Updated 10 years ago
- tokenizer and parser for circle projects☆11Updated 5 years ago
- Verilog AST☆19Updated 11 months ago
- Gate-Level Simulation on a GPU☆9Updated 8 years ago
- Simulation of the classic Pacman arcade game on a PanoLogic thin client.☆32Updated 5 years ago
- A C implementation of the Tsetlin Machine☆14Updated 5 years ago
- This is the universal backend for the Venus project.☆7Updated 2 years ago
- A bit-serial CPU☆18Updated 5 years ago
- Source code for GpuShareSat, a library for SAT solvers to use the GPU for clause sharing between CPU threads.☆32Updated 3 years ago
- Digital/Analog Circuit Design and Simulation System for Windows☆25Updated 5 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 7 years ago
- The PE for the second generation CGRA (garnet).☆16Updated 2 months ago
- Verilog projects for simulation and logic synthesis (Icarus Verilog, YOSYS)☆20Updated 3 years ago
- RISC-V RV64IS-compatible processor for the Kestrel-3☆21Updated last year
- Formal semantics of BSV (Bluespec SystemVerilog), given as a Haskell Program and accompanying document☆18Updated 8 years ago
- Superoptimizer using the z3 SMT solver☆15Updated 3 years ago
- ☆55Updated 2 years ago