smunaut / axi-csi-rx

Related projects: ⓘ

• topic-embedded-products / kernel-module-vdmafb
  VDMA framebuffer driver for LVDS display
  ☆15Updated 7 years ago
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆53Updated this week
• antmicro / usb-test-suite-build
  Cocotb (Python) based USB 1.1 test suite for FPGA IP, with testbenches for a variety of open source USB cores
  ☆49Updated last year
• Elphel / x393_sata
  mirror of https://git.elphel.com/Elphel/x393_sata
  ☆33Updated 4 years ago
• xupsh / Amp-zynq
  Simple AMP Running Linux and Bare-Metal System on Both Zynq SoC Processors
  ☆19Updated 8 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• www-asics-ws / usb1_device
  USB 1.1 Device IP Core
  ☆18Updated 6 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆39Updated 3 months ago
• pulp-platform / adv_dbg_if
  Advanced Debug Interface
  ☆12Updated last year
• iammituraj / FIFOs
  Register-based and RAM-based FIFOs designed in Verilog/System Verilog.
  ☆14Updated last month
• twlostow / urv-core
  uRV RISC-V core
  ☆15Updated 8 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆33Updated 7 years ago
• ThalesGroup / TMR
  Triple Modular Redundancy
  ☆23Updated 5 years ago
• andrewsil1 / NexysPsram
  AXI PSRAM Controller IP for use with Digilent Nexys 4
  ☆10Updated 2 years ago
• lewiz-support / LMAC_CORE1
  LMAC Core1 - Ethernet 1G/100M/10M
  ☆16Updated last year
• Xilinx / revCtrl
  Revision Control Labs and Materials
  ☆23Updated 6 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆35Updated 5 years ago
• BrooksEE / nitro-parts-lib-mipi
  RTL for mipi serialize and deserialize
  ☆11Updated 6 years ago
• pulp-platform / jtag_dpi
  JTAG DPI module for SystemVerilog RTL simulations
  ☆25Updated 8 years ago
• CospanDesign / vivado-ip-cores
  IP Cores that can be used within Vivado
  ☆24Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• TUM-LIS / glip
  Generic Logic Interfacing Project
  ☆44Updated 4 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆45Updated last year
• bluecmd / wb-axi
  Wishbone <-> AXI converters
  ☆11Updated 9 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆35Updated 6 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆22Updated 2 years ago
• maltevesper / JetStream-hardware
  ☆22Updated 8 years ago
• DUNE / pl-nvme
  ☆24Updated 4 years ago
• Xilinx / bootgen
  bootgen source code
  ☆33Updated last month
• subutai-attic / pars
  ☆28Updated 7 years ago