Alternatives and similar repositories for soc

Users that are interested in soc are comparing it to the libraries listed below

• inforichland / freezing-spice
  A pipelined RISCV implementation in VHDL
  ☆96Updated 6 years ago
• cseed / cynth
  a simple C-to-Verilog compiler
  ☆51Updated 8 years ago
• stacksmith / fpgasm
  FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)
  ☆53Updated 4 years ago
• jamesbowman / j1
  The J1 CPU
  ☆171Updated 4 years ago
• inforichland / yafc
  Yet Another Forth Core...
  ☆72Updated 10 years ago
• SRI-CSL / l3riscv
  An executable specification of the RISCV ISA in L3.
  ☆42Updated 6 years ago
• drom / quark
  Stack CPU Work In Progress
  ☆30Updated last year
• zhemao / ez8
  The Easy 8-bit Processor
  ☆183Updated 11 years ago
• mrisc32 / mrisc32
  MRSIC32 ISA documentation and development
  ☆91Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆34Updated 7 years ago
• ujamjar / hardcaml-riscv
  RISC-V instruction set CPUs in HardCaml
  ☆16Updated 8 years ago
• Anding / N.I.G.E.-Machine
  A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…
  ☆28Updated 8 months ago
• JohnDRO / Golirev-IDE
  An online Verilog IDE based on YosysJS.
  ☆24Updated 9 years ago
• CTSRD-CHERI / beri
  The BERI and CHERI processor and hardware platform
  ☆50Updated 8 years ago
• mangpo / chlorophyll
  Synthesis-Aided Compiler for GreenArrays GA144
  ☆53Updated 8 years ago
• jameshegarty / rigel
  Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…
  ☆56Updated 4 years ago
• cornell-brg / pydgin
  A (Py)thon (D)SL for (G)enerating (In)struction set simulators.
  ☆166Updated 7 years ago
• terpstra / opa
  Open Processor Architecture
  ☆26Updated 9 years ago
• SteffenReith / J1Sc
  A reimplementation of a tiny stack CPU
  ☆85Updated last year
• KestrelComputer / S64X7
  64-bit MISC Architecture CPU
  ☆12Updated 8 years ago
• ZipCPU / zbasic
  A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems
  ☆43Updated 2 years ago
• cfelton / alt.hdl
  Exploration of alternative hardware description languages
  ☆28Updated 7 years ago
• tomahawkins / verilog
  A Verilog parser for Haskell.
  ☆36Updated 4 years ago
• kmonachopoulos / Spacecraft-Multicore-Emulator
  Spacecraft Multicore Emulator Based on Leon 3 Sparc V8 architecture processor
  ☆51Updated 6 years ago
• onchipuis / mriscvcore
  A 32-bit RISC-V processor for mriscv project
  ☆58Updated 8 years ago
• azonenberg / antikernel
  The Antikernel operating system project
  ☆121Updated 5 years ago
• jamesbowman / swapforth
  Swapforth is a cross-platform ANS Forth
  ☆292Updated last year
• aeste / aemb
  Multi-threaded 32-bit embedded core family.
  ☆24Updated 13 years ago
• google / autopiper
  ☆47Updated 9 years ago
• knielsen / ice40_viewer
  ☆61Updated last year