combinatorylogic / socLinks
An experimental System-on-Chip with a custom compiler toolchain.
☆60Updated 5 years ago
Alternatives and similar repositories for soc
Users that are interested in soc are comparing it to the libraries listed below
Sorting:
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆54Updated 4 years ago
- A pipelined RISCV implementation in VHDL☆97Updated 6 years ago
- Stack CPU Work In Progress☆30Updated last year
- The J1 CPU☆172Updated 5 years ago
- The BERI and CHERI processor and hardware platform☆49Updated 8 years ago
- Yet Another Forth Core...☆72Updated 11 years ago
- Synthesis-Aided Compiler for GreenArrays GA144☆54Updated 8 years ago
- MRSIC32 ISA documentation and development☆91Updated 2 years ago
- a simple C-to-Verilog compiler☆51Updated 8 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆28Updated last month
- OpenFPGA☆34Updated 7 years ago
- The Antikernel operating system project☆119Updated 5 years ago
- Multi-threaded 32-bit embedded core family.☆24Updated 13 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- An executable specification of the RISCV ISA in L3.☆41Updated 6 years ago
- The Easy 8-bit Processor☆184Updated 11 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- A reimplementation of a tiny stack CPU☆85Updated last year
- A Verilog parser for Haskell.☆36Updated 4 years ago
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 5 years ago
- Swapforth is a cross-platform ANS Forth☆295Updated last year
- Open Processor Architecture☆26Updated 9 years ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆44Updated 3 years ago
- ☆61Updated 2 years ago
- An FPGA microcontroller that natively executes LISP☆94Updated last year
- A (Py)thon (D)SL for (G)enerating (In)struction set simulators.☆167Updated 7 years ago
- Moxie-compatible core repository☆47Updated 3 months ago
- A bit-serial CPU☆19Updated 6 years ago
- Exploration of alternative hardware description languages☆28Updated 7 years ago
- RISC-V instruction set CPUs in HardCaml☆15Updated 9 years ago