combinatorylogic / soc
An experimental System-on-Chip with a custom compiler toolchain.
☆59Updated 5 years ago
Alternatives and similar repositories for soc:
Users that are interested in soc are comparing it to the libraries listed below
- A pipelined RISCV implementation in VHDL☆95Updated 6 years ago
- Stack CPU Work In Progress☆30Updated last year
- FPGA assembler! Create bare-metal FPGA designs without Verilog or VHDL (Not to self: use Lisp next time)☆53Updated 3 years ago
- Yet Another Forth Core...☆71Updated 10 years ago
- a simple C-to-Verilog compiler☆48Updated 7 years ago
- OpenFPGA☆33Updated 6 years ago
- Exploration of alternative hardware description languages☆28Updated 6 years ago
- Open Processor Architecture☆26Updated 8 years ago
- A user-expandable micro-computer system that runs on an FPGA development board and includes the FORTH software language. The system is cu…☆27Updated 2 months ago
- An executable specification of the RISCV ISA in L3.☆41Updated 5 years ago
- firrtlator is a FIRRTL C++ library☆21Updated 8 years ago
- MRSIC32 ISA documentation and development☆90Updated last year
- Synthesis-Aided Compiler for GreenArrays GA144☆52Updated 8 years ago
- The BERI and CHERI processor and hardware platform☆47Updated 7 years ago
- The J1 CPU☆164Updated 4 years ago
- A reimplementation of a tiny stack CPU☆81Updated last year
- Rigel is a language for describing image processing hardware embedded in Lua. Rigel can compile to Verilog hardware designs for Xilinx FP…☆56Updated 4 years ago
- Verilog FPGA Parts Library. Old Octavo soft-CPU project.☆72Updated 5 years ago
- A microcontroller that natively executes a simple LISP dialect☆90Updated last year
- RISC-V instruction set CPUs in HardCaml☆15Updated 8 years ago
- An online Verilog IDE based on YosysJS.☆24Updated 9 years ago
- 64-bit MISC Architecture CPU☆12Updated 8 years ago
- Yet Another VHDL tool☆31Updated 7 years ago
- The Easy 8-bit Processor☆182Updated 10 years ago
- Tools and Examples for IcoBoard☆79Updated 3 years ago
- A 32-bit RISC-V processor for mriscv project☆58Updated 7 years ago
- ☆58Updated last year
- a parallel sorting algorithm implemented in hardware that sorts data in linear time as it arrives serially☆39Updated 9 years ago
- Bachelor thesis Martijn Bakker -- Numerical mathematics on FPGAs using CλaSH☆28Updated 9 years ago
- Single, dual, quad, eight, and sixteen-shader GP-GPU-Compute engines, along with 32-bit SYMPL RISC CPU and Coarse-Grained Scheduler, in o…☆22Updated 6 years ago