An experimental System-on-Chip with a custom compiler toolchain.
☆60Jan 2, 2020Updated 6 years ago
Alternatives and similar repositories for soc
Users that are interested in soc are comparing it to the libraries listed below
Sorting:
- FPGA Development toolset☆20Jun 15, 2017Updated 8 years ago
- 1st Testwafer for LibreSilicon☆15May 24, 2019Updated 6 years ago
- SwapForth J1a processor for Icestudio☆12Aug 28, 2020Updated 5 years ago
- A Forth J1 emulator in C☆13Nov 25, 2025Updated 3 months ago
- Information on cores available on the Ulx3s ECP5 FPGA board☆14May 1, 2020Updated 5 years ago
- iCE40 floorplan viewer☆24Jun 23, 2018Updated 7 years ago
- A pipelined RISCV implementation in VHDL☆96Nov 19, 2018Updated 7 years ago
- ☆61Oct 10, 2023Updated 2 years ago
- For exploring http://www.ioccc.org/2012/tromp/hint.html☆35Aug 2, 2017Updated 8 years ago
- 32-bit RISC-V system on chip for iCE40 FPGAs☆313May 25, 2023Updated 2 years ago
- Featherweight RISC-V implementation☆53Jan 17, 2022Updated 4 years ago
- The J1 CPU☆173Oct 14, 2020Updated 5 years ago
- An executable specification of the RISCV ISA in L3.☆42Mar 1, 2019Updated 7 years ago
- eForth for the j1 simulator and actual J1 FPGAs☆38Mar 31, 2015Updated 10 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100May 16, 2019Updated 6 years ago
- The Kent Retargetable occam Compiler☆46Feb 19, 2022Updated 4 years ago
- A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs☆63Jan 8, 2019Updated 7 years ago
- Pipelined DCPU-16 Verilog Implementation☆42May 30, 2012Updated 13 years ago
- Experimental, high-performance GPU-accelerated rasterizer for common Web content☆11Jul 16, 2015Updated 10 years ago
- VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs☆52Jan 19, 2021Updated 5 years ago
- Repository containing the DSP gateware cores☆14Feb 6, 2026Updated 3 weeks ago
- Firmware for Xilinx Platform Cable 1 USB Jtag adapter☆10Jul 24, 2016Updated 9 years ago
- Resources from my class on computer architecture design☆10Apr 25, 2018Updated 7 years ago
- ChipScope / ILA using XVC (XIlinx Virtual Cable Over PCIe) with a PR (Partial Reconfiguration) design Example.☆14Jun 1, 2017Updated 8 years ago
- HLS implementation of cuckoo hashing. Refer to paper : https://ieeexplore.ieee.org/document/7577355/☆14Dec 4, 2018Updated 7 years ago
- GeekGameBoard (GGB) is a small framework for building board and card games. It's based on Apple's Core Animation framework.☆21Mar 14, 2013Updated 12 years ago
- Unofficial wrapper of the IAU SOFA C libraries for fundamental astronomy.☆10Jan 7, 2021Updated 5 years ago
- A crackme demo program based on Forth code☆13Sep 27, 2012Updated 13 years ago
- RISC-V System on Chip Builder☆12Sep 27, 2020Updated 5 years ago
- Code which loads custom ISA on Intel Haswell GPUs☆47Sep 12, 2016Updated 9 years ago
- Open source fpga project leveraging vtr CAD flow.☆26Mar 4, 2023Updated 2 years ago
- Swapforth is a cross-platform ANS Forth☆299Dec 26, 2023Updated 2 years ago
- Verilog modules for software-defined radio.☆18Dec 31, 2012Updated 13 years ago
- Standard HyperRAM core for ECP5 written in Litex/Migen☆14Dec 6, 2019Updated 6 years ago
- Simulations and designs for bit serial ALU implemented in TTL circuitry. Also bit serial cpu architectures - all simulated using H. Neem…☆12Aug 26, 2022Updated 3 years ago
- CamelForth in C for RP2040 Raspberry Pi Pico. A Forth by Dr Brad Rodriguez - ported to RP2040 by wa1tnr - Forth interpreter is on the RP2…☆12Oct 27, 2021Updated 4 years ago
- A cross platform, formally verified, open source, hyperRAM controller with simulator☆14Feb 22, 2019Updated 7 years ago
- The Programmers Open Workbench☆13Dec 19, 2011Updated 14 years ago
- Port of Amber ARM Core project to Marsohod2 platform☆13Dec 4, 2019Updated 6 years ago