RIOSLaboratory / Open3DFlow
An open-source 3D IC design platform that leverages existing open EDA tools while incorporating tailored abstractions and customizations optimized for 3D chiplet designs.
☆25Updated 5 months ago
Alternatives and similar repositories for Open3DFlow:
Users that are interested in Open3DFlow are comparing it to the libraries listed below
- A toolchain for rapid design space exploration of chiplet architectures☆45Updated this week
- An Open-Source Analytical Placer for Large Scale Heterogeneous FPGAs using Deep-Learning Toolkit☆81Updated 3 months ago
- A list of our chiplet simulaters☆32Updated 3 weeks ago
- Dataset for ML-guided Accelerator Design☆36Updated 5 months ago
- The open-sourced version of BOOM-Explorer☆39Updated last year
- The first version of TritonPart☆26Updated last year
- ☆30Updated 3 years ago
- ☆16Updated 3 years ago
- MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design☆45Updated 7 months ago
- Collection of digital hardware modules & projects (benchmarks)☆54Updated 5 months ago
- ☆25Updated last year
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆34Updated 2 weeks ago
- ☆38Updated 2 years ago
- Ratatoskr NoC Simulator☆24Updated 4 years ago
- [DATE 2022] PowerGear: Early-Stage Power Estimation in FPGA HLS via Heterogeneous Edge-Centric GNNs☆17Updated 3 years ago
- ☆29Updated last year
- CATCH 1.0, Initial full release of CATCH cost model.☆14Updated 2 months ago
- A low power platform based on X-HEEP and integrating the ESL-CGRA☆14Updated 6 months ago
- An integrated CGRA design framework☆87Updated last month
- SAURIA (Systolic-Array tensor Unit for aRtificial Intelligence Acceleration) is an open-source Convolutional Neural Network accelerator b…☆39Updated 6 months ago
- Template-based Reconfigurable Architecture Modeling Framework☆14Updated 2 years ago
- This is a python repo for flattening Verilog☆16Updated 2 weeks ago
- An Open-Hardware CGRA for accelerated computation on the edge.☆24Updated 7 months ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆74Updated 3 years ago
- ☆22Updated 10 months ago
- Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)☆50Updated 3 months ago
- Runtime-First FPGA Interchange Routing Contest @ FPGA’24☆33Updated 2 months ago
- CGRA framework with vectorization support.☆29Updated this week
- PANDA: Architecture-Level Power Evaluation by Unifying Analytical and Machine Learning Solutions☆15Updated last year
- ☆71Updated 4 months ago