Quarky93 / warpshellLinks
☆17Updated 2 years ago
Alternatives and similar repositories for warpshell
Users that are interested in warpshell are comparing it to the libraries listed below
Sorting:
- An energy-efficient RISC-V floating-point compute cluster.☆111Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 3 months ago
- ☆79Updated this week
- ☆30Updated 3 weeks ago
- For contributions of Chisel IP to the chisel community.☆66Updated 11 months ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated last month
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆42Updated 2 years ago
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆91Updated last month
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆137Updated this week
- ☆147Updated 2 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆180Updated this week
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆141Updated last week
- ASIC implementation flow infrastructure☆132Updated this week
- Chisel Fixed-Point Arithmetic Library☆16Updated 9 months ago
- A Fast, Low-Overhead On-chip Network☆228Updated this week
- RISC-V Formal Verification Framework☆153Updated this week
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆90Updated last month
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆182Updated 3 weeks ago
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago
- Open-source RTL logic simulator with CUDA acceleration☆222Updated 2 weeks ago
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated last year
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- ☆80Updated last year
- ☆108Updated 2 months ago
- A Hardware Implemented Poseidon Hasher☆18Updated 3 years ago
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆127Updated 2 years ago
- Verilog package manager written in Rust☆143Updated last year
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated 5 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆66Updated 3 weeks ago