Quarky93 / warpshellLinks
☆17Updated 2 years ago
Alternatives and similar repositories for warpshell
Users that are interested in warpshell are comparing it to the libraries listed below
Sorting:
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆19Updated 2 years ago
- An energy-efficient RISC-V floating-point compute cluster.☆118Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 5 months ago
- ☆89Updated last week
- Self checking RISC-V directed tests☆118Updated 6 months ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆178Updated this week
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆205Updated last week
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆43Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆75Updated last month
- Vector processor for RISC-V vector ISA☆133Updated 5 years ago
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆155Updated last week
- For contributions of Chisel IP to the chisel community.☆70Updated last year
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆94Updated 3 weeks ago
- AXI Adapter(s) for RISC-V Atomic Operations☆66Updated 2 weeks ago
- ☆120Updated 4 months ago
- ☆71Updated last week
- The multi-core cluster of a PULP system.☆109Updated last month
- Open-source RTL logic simulator with CUDA acceleration☆244Updated 2 months ago
- RISC-V Formal Verification Framework☆170Updated last week
- A Fast, Low-Overhead On-chip Network☆255Updated last week
- Main page☆129Updated 5 years ago
- wellen: waveform datastructures in Rust. Fast VCD, FST and GHW parsing for waveform viewers.☆103Updated this week
- A Style Guide for the Chisel Hardware Construction Language☆108Updated 4 years ago
- Verilog package manager written in Rust☆143Updated last year
- The Task Parallel System Composer (TaPaSCo)☆115Updated last week
- Fabric generator and CAD tools.☆214Updated this week
- The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.☆124Updated 5 months ago
- Generic Register Interface (contains various adapters)☆134Updated last month
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆112Updated last month
- Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and a…☆114Updated 2 years ago