Quarky93 / warpshell
☆16Updated last year
Alternatives and similar repositories for warpshell:
Users that are interested in warpshell are comparing it to the libraries listed below
- Hardcaml_zprize implements high performance, open source cryptographic solutions for large scale number theoretic transforms (NTT) and mu…☆54Updated 8 months ago
- FPT: a Fixed-Point Accelerator for Torus Fully Homomorphic Encryption☆17Updated 6 months ago
- RISC-V Formal Verification Framework☆127Updated last month
- Tests for example Rocket Custom Coprocessors☆69Updated 5 years ago
- A Style Guide for the Chisel Hardware Construction Language☆107Updated 3 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆18Updated 4 years ago
- A Hardware Implemented Poseidon Hasher☆18Updated 2 years ago
- A configurable SRAM generator☆42Updated last month
- [FPGA 2022, Best Paper Award] Parallel placement and routing of Vivado HLS dataflow designs.☆119Updated 2 years ago
- A GPU acceleration flow for RTL simulation with batch stimulus☆102Updated 10 months ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆29Updated last year
- Proposed RISC-V Composable Custom Extensions Specification☆69Updated 9 months ago
- Chisel Learning Journey☆108Updated last year
- ☆27Updated 2 months ago
- Advanced Architecture Labs with CVA6☆54Updated last year
- ☆15Updated last year
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆92Updated this week
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 4 years ago
- Chisel module for performing Multi-Scalar Multiplication☆12Updated 2 years ago
- Examples for creating AXI-interfaced peripherals in Chisel☆74Updated 9 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆75Updated 10 months ago
- high-performance RTL simulator☆152Updated 8 months ago
- For contributions of Chisel IP to the chisel community.☆59Updated 3 months ago
- ☆32Updated 4 months ago
- This tools offer many simulation of memory design detail parameter. Then you can setting these parameter to running result in your condit…☆14Updated 8 years ago
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆156Updated last month
- AXI Adapter(s) for RISC-V Atomic Operations☆60Updated 5 months ago
- Chisel components for FPGA projects☆120Updated last year
- Zcash FPGA acceleration engine☆121Updated 4 years ago