☆15Nov 26, 2024Updated last year
Alternatives and similar repositories for stripes
Users that are interested in stripes are comparing it to the libraries listed below
Sorting:
- The official repository of metro-mpi☆17Sep 3, 2025Updated 6 months ago
- Examples of how to Generate Schematics from SystemVerilog Synthesis Tools☆22Dec 22, 2023Updated 2 years ago
- Cohort Project☆19Oct 23, 2025Updated 4 months ago
- MAPLE's hardware-software co-design allows programs to perform long-latency memory accesses asynchronously from the core, avoiding pipeli…☆21Feb 22, 2024Updated 2 years ago
- Control Logic Synthesis: Drawing the Rest of the OWL☆13Jun 17, 2024Updated last year
- ☆20Feb 19, 2026Updated 2 weeks ago
- ☆22Mar 28, 2023Updated 2 years ago
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 4 years ago
- Hardware implementation of a Fixed Point Recursive Forward and Inverse FFT algorithm☆16Mar 3, 2018Updated 8 years ago
- Parse all of your facebook messages - updated to work on the newest formatting of Facebook Data (Jan 2026).☆12Jan 19, 2026Updated last month
- ☆11Mar 22, 2022Updated 3 years ago
- Rust proof-of-concept for GPU waveform rendering☆13Jul 22, 2020Updated 5 years ago
- Implementations of the classification algorithm "Adaboost" with various weak learners☆11Aug 25, 2017Updated 8 years ago
- ☆17Oct 15, 2023Updated 2 years ago
- ☆10Feb 13, 2025Updated last year
- Scans posts you haven't yet seen in your mastodon timeline and sends the most popular ones to your inbox☆13Jan 5, 2023Updated 3 years ago
- A D-Bus MPRIS daemon for controlling media players.☆15Jul 18, 2025Updated 7 months ago
- Simulation infrastructure and validation of Cori☆13Mar 22, 2022Updated 3 years ago
- [ACL'25] Code for ACL'25 paper "IRT-Router: Effective and Interpretable Multi-LLM Routing via Item Response Theory"☆26Feb 19, 2025Updated last year
- A git repo that is creepy☆15Sep 14, 2020Updated 5 years ago
- Multiple approaches to statistical simulation for computer architects☆15Jun 1, 2020Updated 5 years ago
- 586 compatible soft core for FPGA in verilog with AXI4 interface☆15Oct 15, 2016Updated 9 years ago
- ☆14Feb 28, 2023Updated 3 years ago
- An open-source simulator framework for neural processing units☆37Jan 30, 2026Updated last month
- What if everything is a io_uring?☆17Nov 10, 2022Updated 3 years ago
- LEN5 is a configurable, speculative, out-of-order, 64-bit RISC-V microprocessor targetting etherogeneus systems on chip.☆19Oct 22, 2025Updated 4 months ago
- ☆15Jun 18, 2024Updated last year
- OBI SystemVerilog synthesizable interconnect IPs for on-chip communication☆19Jan 9, 2026Updated last month
- E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis (DAC2025)☆28Jun 23, 2025Updated 8 months ago
- Workshop on getting better at vim☆24Jan 13, 2026Updated last month
- Save information about traffic to a GitHub repository☆22Aug 31, 2017Updated 8 years ago
- The OpenPiton Platform☆17Aug 14, 2024Updated last year
- Quick'n'dirty FuseSoC+cocotb example☆19Nov 26, 2024Updated last year
- ☆23Apr 9, 2024Updated last year
- This repository provides supplementary material for our paper HiFi-DRAM: Enabling High-fidelity DRAM Research by Uncovering Sense Amplifi…☆20May 8, 2024Updated last year
- ☆20Oct 27, 2022Updated 3 years ago
- Implementation of FlexSC on Linux Kernel v5.0+ and Performance Analysis☆19Mar 15, 2020Updated 5 years ago
- Alogic is a Medium Level Synthesis language for digital logic that compiles swiftly into standard Verilog-2005 for implementation in ASIC…☆18May 19, 2021Updated 4 years ago
- ☆20Jun 7, 2024Updated last year