EECS-NTNU / chipyard
Pre-release starter template for custom Chisel projects
☆9Updated last month
Alternatives and similar repositories for chipyard
Users that are interested in chipyard are comparing it to the libraries listed below
Sorting:
- ☆25Updated last year
- Simulator framework for analysis of performance, energy consumption, area and cost of multi-node multi-chiplet tile-based manycore design…☆65Updated 10 months ago
- ☆20Updated 2 years ago
- An alternative Vivado custom design example (to fully Vitis) for the User Logic Partition targeting VCK5000☆12Updated 10 months ago
- ☆40Updated 4 months ago
- ☆15Updated 2 years ago
- ☆23Updated 4 years ago
- Domain-Specific Architecture Generator 2☆21Updated 2 years ago
- ArchExplorer: Microarchitecture Exploration Via Bottleneck Analysis☆31Updated last year
- ☆14Updated 2 years ago
- [FPGA'21] Microbenchmarks for Demystifying the Memory System of Modern Datacenter FPGAs for Software Programmers☆30Updated 3 years ago
- A Scalable BFS Accelerator on FPGA-HBM Platform☆14Updated last year
- ☆10Updated 2 years ago
- CGRA framework with vectorization support.☆29Updated last week
- The RAD flow is an open-source academic architecture exploration and evaluation flow for novel beyond-FPGA reconfigurable acceleration de…☆34Updated last month
- A simple MIPS-like CPU demo in C++ for Xilinx Vivado HLS☆18Updated 5 years ago
- ☆30Updated last month
- ☆27Updated 6 months ago
- ☆14Updated 2 years ago
- STONNE Simulator integrated into SST Simulator☆19Updated last year
- ☆25Updated 3 years ago
- ☆35Updated 4 years ago
- ☆11Updated 2 weeks ago
- ☆13Updated last year
- A list of our chiplet simulaters☆32Updated last month
- DASS HLS Compiler☆29Updated last year
- HLS for Networks-on-Chip☆34Updated 4 years ago
- ☆51Updated last month
- The simulator for SPADA, an SpGEMM accelerator with adaptive dataflow☆37Updated 2 years ago
- Accelerating SSSP for power-law graphs using an FPGA.☆23Updated 3 years ago