ysyx-org / jemu-decoderLinks
The decoder library for jemu execution and web documentation
☆54Updated 2 years ago
Alternatives and similar repositories for jemu-decoder
Users that are interested in jemu-decoder are comparing it to the libraries listed below
Sorting:
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆175Updated 4 years ago
- PLCT工具箱☆31Updated 3 years ago
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆117Updated 11 months ago
- Super fast RISC-V ISA emulator for XiangShan processor☆295Updated this week
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆194Updated last year
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆49Updated 3 weeks ago
- Modern co-simulation framework for RISC-V CPUs☆158Updated this week
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated this week
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- 一生 一芯的信息发布和内容网站☆135Updated last year
- 体系结构研讨 + ysyx高阶大纲 (WIP☆181Updated last year
- An exquisite superscalar RV32GC processor.☆161Updated 9 months ago
- A translation project of the RISC-V reader☆174Updated last year
- CQU Dual Issue Machine☆37Updated last year
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated last year
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆49Updated last year
- VSH(SHell for Visualizing vcd file)项目为数字波形文件命令行查看器。☆24Updated last week
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- ☆56Updated last week
- ☆40Updated 2 years ago
- Official website for Jiachen Project (甲辰计划).☆59Updated last month
- 龙芯杯21个人赛作品☆35Updated 4 years ago
- Linux-capable in-order superscaler LoongArch32r processor. Silicon-proven.☆45Updated last year
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆39Updated 2 years ago
- ☆67Updated last year
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆82Updated 2 years ago
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆231Updated 4 years ago
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆31Updated 6 months ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆32Updated last year
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago