ysyx-org / jemu-decoderLinks
The decoder library for jemu execution and web documentation
☆54Updated 2 years ago
Alternatives and similar repositories for jemu-decoder
Users that are interested in jemu-decoder are comparing it to the libraries listed below
Sorting:
- A simple full system emulator. Currently support RV64IMACSU and MIPS32 and LoongArch32. Capable of booting Linux. Suitable for education …☆119Updated last year
- PLCT工具箱☆30Updated 3 years ago
- Super fast RISC-V ISA emulator for XiangShan processor☆308Updated this week
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆51Updated last month
- Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.☆182Updated 4 years ago
- A translation project of the RISC-V reader☆173Updated 2 years ago
- This is a repo for recording and reporting RISCV platform's test and measurement continuously.☆59Updated 2 years ago
- A superscalar RISC-V CPU with out-of-order execution and multi-core support☆61Updated 3 years ago
- A RISC-V core running Debian (and a LoongArch core running Linux).☆22Updated 2 months ago
- Modern co-simulation framework for RISC-V CPUs☆171Updated this week
- 《从零开始的RISC-V模拟器开发》配套的PPT和教学资料☆234Updated 4 years ago
- A Simple RISC-V CPU Simulator with 5 Stage Pipeline, Branch Prediction and Cache Simulation☆200Updated last year
- CQU Dual Issue Machine☆38Updated last year
- ☆65Updated last month
- 💻 RISC-V Simulator of RV32I ISA. 5-stage pipeline / out-of-order execution with Tomasulo algorithm and Speculation. Support runtime visu…☆206Updated 5 years ago
- An exquisite superscalar RV32GC processor.☆165Updated last year
- A simple and fast RISC-V JIT emulator.☆155Updated last year
- 一生一芯的信息发布和内容网站☆136Updated 2 years ago
- PLCT实验室维护的QEMU仓库。代码放在 plct- 前缀的分支里。☆30Updated 4 months ago
- RISC-V模拟器,相关硬件实现`riscv-isa-sim`以及模拟器pk, bbl的指导手册☆53Updated 5 years ago
- 体系结构研讨 + ysyx高阶大纲 (WIP☆195Updated last year
- A tool to decode RISC-V and LoongArch and MIPS instructions in gtkwave☆32Updated 9 months ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆40Updated 2 years ago
- PLCT实验室的 RISC-V V Spec 实现,基于llvm/llvm-project,rkruppe/rvv-llvm 和 https://repo.hca.bsc.es/gitlab/rferrer/llvm-epi-0.8☆161Updated 5 months ago
- 第一届 RISC-V 中国峰会的幻灯片等资料存放☆38Updated 3 years ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆50Updated 2 years ago
- 第六届龙芯杯混元形意太极门战队作品☆18Updated 3 years ago
- RISC-V Summit China 2023☆40Updated 2 years ago
- Official website for Jiachen Project (甲辰计划).☆62Updated this week
- Documentation for XiangShan Design☆41Updated last week