Alternatives and similar repositories for Tethorax

Users that are interested in Tethorax are comparing it to the libraries listed below

• bol-edu / caravel-soc
  ☆30Updated 2 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆186Updated last month
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆303Updated 8 months ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆329Updated 10 months ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆157Updated 6 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆605Updated 2 weeks ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆302Updated 3 weeks ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆160Updated last year
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• chipsalliance / Cores-VeeR-EH2
  ☆245Updated 2 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆278Updated 2 weeks ago
• pulp-platform / pulp-riscv-gnu-toolchain
  ☆96Updated 2 months ago
• dineshannayya / riscduino
  Arduino compatible Risc-V Based SOC
  ☆157Updated last year
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆218Updated 5 years ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆360Updated 8 months ago
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆428Updated 2 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆389Updated 4 months ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆143Updated last year
• riscv-non-isa / riscv-arch-test
  ☆601Updated this week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 5 months ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 11 months ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆223Updated 8 months ago
• PulseRain / Reindeer
  PulseRain Reindeer - RISCV RV32I[M] Soft CPU
  ☆127Updated 6 years ago
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆370Updated last year
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆667Updated last month
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆327Updated 2 weeks ago
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆129Updated 5 years ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆186Updated 2 weeks ago
• pulp-platform / clic
  RISC-V fast interrupt controller
  ☆29Updated 2 weeks ago