Alternatives and similar repositories for Tethorax

Users that are interested in Tethorax are comparing it to the libraries listed below

• bol-edu / caravel-soc
  ☆30Updated 2 years ago
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• sameersondur / VHDL-Project-16-bit-RISC-Processor
  Designed a RISC processor with 16 bit instruction set, 4-stage pipeline and a non-pre-emptive interrupt handler. Implemented it in VHDL a…
  ☆19Updated 11 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• openhwgroup / core-v-verif
  Functional verification project for the CORE-V family of RISC-V cores.
  ☆614Updated last month
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆277Updated 5 years ago
• XUANTIE-RV / opene902
  OpenXuantie - OpenE902 Core
  ☆161Updated last year
• os-fpga / open-source-fpga-resource
  A list of resources related to the open-source FPGA projects
  ☆433Updated 2 years ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆306Updated 9 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• RTimothyEdwards / tutorial_layout
  Repository of files associated with the webinar on analog layout using magic and klayout with Matt Venn.
  ☆15Updated 2 years ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆219Updated 5 years ago
• litex-hub / linux-on-litex-vexriscv
  Linux on LiteX-VexRiscv
  ☆665Updated 2 months ago
• chipsalliance / Cores-VeeR-EH2
  ☆247Updated 2 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆129Updated 7 years ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆435Updated last week
• pulp-platform / pulpissimo
  This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…
  ☆446Updated 6 months ago
• skordal / potato
  A simple RISC-V processor for use in FPGA designs.
  ☆282Updated last year
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆102Updated last week
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 8 months ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆197Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆281Updated last week
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆160Updated 6 years ago
• riscv-non-isa / riscv-arch-test
  ☆609Updated this week
• mongrelgem / RISCY
  Simple RISC-V RV32I CPU in VHDL for use in FPGA Designs
  ☆16Updated 6 years ago
• chipsalliance / Cores-VeeR-EH1
  VeeR EH1 core
  ☆910Updated 2 years ago
• lowRISC / style-guides
  lowRISC Style Guides
  ☆466Updated 2 weeks ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆115Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆246Updated last year
• XUANTIE-RV / openc906
  OpenXuantie - OpenC906 Core
  ☆372Updated last year