bol-edu / caravel-soc
☆28Updated last year
Alternatives and similar repositories for caravel-soc:
Users that are interested in caravel-soc are comparing it to the libraries listed below
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- AMBA bus generator including AXI, AHB, and APB☆96Updated 3 years ago
- ☆40Updated 2 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆62Updated 4 years ago
- AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc☆36Updated 2 years ago
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆50Updated this week
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆31Updated 2 years ago
- ☆29Updated 5 years ago
- Generic AXI to AHB bridge☆16Updated 10 years ago
- Two Level Cache Controller implementation in Verilog HDL☆39Updated 4 years ago
- General Purpose AXI Direct Memory Access☆48Updated 9 months ago
- SystemVerilog modules and classes commonly used for verification☆45Updated last month
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆13Updated 10 years ago
- HYF's high quality verilog codes☆11Updated last month
- AHB DMA 32 / 64 bits☆52Updated 10 years ago
- ☆15Updated last month
- ☆16Updated 2 years ago
- Xilinx AXI VIP example of use☆33Updated 3 years ago
- 128KB AXI cache (32-bit in, 256-bit out)☆48Updated 3 years ago
- ☆57Updated 9 years ago
- UART -> AXI Bridge☆60Updated 3 years ago
- SoC Based on ARM Cortex-M3☆27Updated last month
- PCIE 5.0 Graduation project (Verification Team)☆61Updated last year
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆73Updated 6 years ago
- RISC-V RV32IMAFC Core for MCU☆36Updated 2 weeks ago
- Asynchronous fifo in verilog☆32Updated 8 years ago
- RTL Verilog library for various DSP modules☆84Updated 3 years ago
- Synopsys Design compiler, VCS and Tetra-MAX☆17Updated 6 years ago
- LCAI-TIHU HW is an AI inference processor which is comprised of RISC-V cpu, nvdla, NoC bus, PCIe module, DDR, SRAM, bootROM, DMA and peri…☆36Updated 2 years ago