bol-edu / caravel-socLinks
☆28Updated 2 years ago
Alternatives and similar repositories for caravel-soc
Users that are interested in caravel-soc are comparing it to the libraries listed below
Sorting:
- AXI4 and AXI4-Lite interface definitions☆93Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆102Updated last year
- This is the repository for the IEEE version of the book☆66Updated 4 years ago
- AHB3-Lite Interconnect☆90Updated last year
- PCIE 5.0 Graduation project (Verification Team)☆79Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆161Updated last month
- Basic RISC-V Test SoC☆137Updated 6 years ago
- Some useful documents of Synopsys☆76Updated 3 years ago
- This is a detailed SystemVerilog course☆113Updated 4 months ago
- RTL Verilog library for various DSP modules☆90Updated 3 years ago
- AXI DMA 32 / 64 bits☆115Updated 11 years ago
- ☆87Updated 10 months ago
- Network on Chip Implementation written in SytemVerilog☆185Updated 2 years ago
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆209Updated 2 years ago
- ☆56Updated 2 years ago
- ☆161Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆170Updated 8 months ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆39Updated 2 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆132Updated 5 years ago
- Asynchronous fifo in verilog☆35Updated 9 years ago
- Course content for the University of Bristol Design Verification course.☆58Updated 9 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆99Updated last year
- SDRAM controller with AXI4 interface☆94Updated 5 years ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- ☆18Updated 3 months ago
- ☆67Updated 9 years ago
- A Fast, Low-Overhead On-chip Network☆215Updated this week
- SystemVerilog Direct Programming Interface (DPI) Tutorial☆65Updated 4 years ago
- RISC-V Verification Interface☆97Updated last month