bol-edu / caravel-socLinks
☆30Updated 2 years ago
Alternatives and similar repositories for caravel-soc
Users that are interested in caravel-soc are comparing it to the libraries listed below
Sorting:
- AXI4 and AXI4-Lite interface definitions☆97Updated 5 years ago
- This is a detailed SystemVerilog course☆127Updated 8 months ago
- AMBA bus generator including AXI, AHB, and APB☆108Updated 4 years ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆117Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆180Updated 2 months ago
- ☆71Updated 9 years ago
- Basic RISC-V Test SoC☆160Updated 6 years ago
- Network on Chip Implementation written in SytemVerilog☆194Updated 3 years ago
- AXI DMA 32 / 64 bits☆122Updated 11 years ago
- Simple cache design implementation in verilog☆53Updated 2 years ago
- A PULP SoC for education, easy to understand and extend with a full flow for a physical design.☆165Updated this week
- Asynchronous fifo in verilog☆37Updated 9 years ago
- PCIE 5.0 Graduation project (Verification Team)☆88Updated last year
- AHB3-Lite Interconnect☆96Updated last year
- A Fast, Low-Overhead On-chip Network☆243Updated this week
- HYF's high quality verilog codes☆16Updated 11 months ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆83Updated 7 years ago
- HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…☆108Updated 2 years ago
- RTL Verilog library for various DSP modules☆92Updated 3 years ago
- A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple mas…☆42Updated 3 years ago
- Two Level Cache Controller implementation in Verilog HDL☆53Updated 5 years ago
- PCI express simulation framework for Cocotb☆181Updated 2 months ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆181Updated last year
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni☆135Updated 7 years ago
- A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.☆138Updated 5 years ago
- UART -> AXI Bridge☆63Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆126Updated last month
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- This is the repository for the IEEE version of the book☆75Updated 5 years ago