Alternatives and similar repositories for VHDL-Project-16-bit-RISC-Processor

Users that are interested in VHDL-Project-16-bit-RISC-Processor are comparing it to the libraries listed below

• hamsternz / simple-riscv
  A simple three-stage RISC-V CPU
  ☆24Updated 4 years ago
• jbush001 / PASC
  Parallel Array of Simple Cores. Multicore processor.
  ☆99Updated 6 years ago
• AleksandarKostovic / Riscy-SoC
  Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog
  ☆80Updated 6 years ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆58Updated last week
• nicolavianello95 / RISC-V
  Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…
  ☆16Updated 5 years ago
• maikmerten / spu32
  Small Processing Unit 32: A compact RV32I CPU written in Verilog
  ☆69Updated 3 years ago
• wyvernSemi / pcievhost
  PCIe (1.0a to 2.0) Virtual Root Complex model for Verilog, with Endpoint capabilities
  ☆114Updated 2 weeks ago
• aignacio / riscv_verilator_model
  RISCV model for Verilator/FPGA targets
  ☆53Updated 5 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆123Updated 4 years ago
• ataradov / riscv
  Verilog implementation of a RISC-V core
  ☆125Updated 7 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆71Updated 5 years ago
• open-design / riscv-soc-cores
  ☆39Updated 4 years ago
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆74Updated 2 years ago
• qmn / riscv-invicta
  A simple RISC-V core, described with Verilog
  ☆26Updated 12 years ago
• rsnikhil / RISCV_Piccolo_v1
  Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).
  ☆34Updated 9 years ago
• SpinalHDL / VexRiscvSoftcoreContest2018
  ☆63Updated 6 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 6 months ago
• SanDisk-Open-Source / riscv-fw-infrastructure
  Firmware infrastructure, contain RTOS Abstraction Layer, demos and more...
  ☆54Updated 3 years ago
• texane / vpcie
  implement PCIE devices using C or VHDL and test them against a QEMU virtualized architecture
  ☆106Updated 7 years ago
• ZipCPU / openarty
  An Open Source configuration of the Arty platform
  ☆133Updated last year
• haojunliu / OpenFPGA
  OpenFPGA
  ☆33Updated 7 years ago
• illustris / FreeRTOS-RISCV
  A port of FreeRTOS for the RISC-V ISA
  ☆77Updated 6 years ago
• ZipCPU / autofpga
  A utility for Composing FPGA designs from Peripherals
  ☆185Updated 9 months ago
• optimsoc / optimsoc
  OpTiMSoC - A tiled SoC platform with a mesh NoC and OpenRISC CPU cores
  ☆85Updated 4 years ago
• chipsalliance / omnixtend
  OmniXtend cache coherence protocol
  ☆82Updated 4 months ago
• PeterAaser / RISCV-FiveStage
  Marginally better than redstone
  ☆100Updated 5 years ago
• eliaskousk / parallella-riscv
  RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards
  ☆103Updated 6 years ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆102Updated 4 years ago
• verilator / example-systemverilog
  ☆40Updated last year
• csail-csg / riscy
  Riscy Processors - Open-Sourced RISC-V Processors
  ☆73Updated 6 years ago