Alternatives and similar repositories for QuantumComputation_FPGAs

Users that are interested in QuantumComputation_FPGAs are comparing it to the libraries listed below

• pulp-platform / svase
  ☆32Updated 9 months ago
• FPGA-Research / FABulous
  Fabric generator and CAD tools.
  ☆197Updated last week
• lsils / lstools-showcase
  Showcase examples for EPFL logic synthesis libraries
  ☆198Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆165Updated last week
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆50Updated last week
• RTimothyEdwards / qflow
  Qflow full end-to-end digital synthesis flow for ASIC designs
  ☆217Updated 11 months ago
• marcelwa / aigverse
  A Python library for working with logic networks, synthesis, and optimization.
  ☆65Updated last week
• lip6 / coriolis
  Coriolis VLSI EDA Tool (LIP6)
  ☆72Updated this week
• woset-workshop / woset-workshop.github.io
  Workshop on Open-Source EDA Technology (WOSET)
  ☆48Updated 11 months ago
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆214Updated 7 months ago
• idea-fasoc / OpenFASOC
  Fully Open Source FASOC generators built on top of open-source EDA tools
  ☆293Updated 3 months ago
• chipsalliance / silicon-notebooks
  ☆172Updated 2 years ago
• pulp-platform / croc
  A PULP SoC for education, easy to understand and extend with a full flow for a physical design.
  ☆144Updated 2 weeks ago
• asyncvlsi / act
  ACT hardware description language and core tools.
  ☆120Updated last week
• ncsu-eda / FreePDK3
  ☆177Updated 4 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆111Updated 4 years ago
• efabless / openlane2
  The next generation of OpenLane, rewritten from scratch with a modular architecture
  ☆315Updated 7 months ago
• efabless / chipignite-resources
  ☆84Updated 2 years ago
• artecs-group / PERCIVAL
  Open-Source Posit RISC-V Core with Quire Capability
  ☆66Updated 8 months ago
• efabless / caravel_user_project
  https://caravel-user-project.readthedocs.io
  ☆221Updated 7 months ago
• siliconcompiler / scgallery
  SiliconCompiler Design Gallery
  ☆51Updated this week
• pulp-platform / carfield
  A mixed-criticality platform built around Cheshire, with a number of safety/security and predictability features. Ready-to-use FPGA flow …
  ☆112Updated 3 months ago
• esl-epfl / x-heep
  eXtendable Heterogeneous Energy-Efficient Platform based on RISC-V
  ☆216Updated last week
• efabless / volare
  Version manager (and builder) for the Google sky130 and gf180mcu open-source PDKs
  ☆73Updated 2 months ago
• efabless / caravel
  Caravel is a standard SoC template with on chip resources to control and read/write operations from a user-dedicated space.
  ☆356Updated 7 months ago
• supadupaplex / pfecap
  Verilog-A Preisach ferroelectric cap (PFECAP) simulation model for FET
  ☆27Updated 5 years ago
• dan-fritchman / Hdl21
  Hardware Description Library
  ☆84Updated 6 months ago
• pkuzjx / eda-collection
  ☆106Updated 5 years ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated last year
• mflowgen / freepdk-45nm
  ASIC Design Kit for FreePDK45 + Nangate for use with mflowgen
  ☆189Updated 5 years ago