MakarenaLabs / Common-PL-Devices-on-PYNQLinks
Integration on PL side of Zynq7000 for PYNQ framework of common industrial devices (GPIO, I2C, SPI and UART)
☆38Updated 4 years ago
Alternatives and similar repositories for Common-PL-Devices-on-PYNQ
Users that are interested in Common-PL-Devices-on-PYNQ are comparing it to the libraries listed below
Sorting:
- PYNQ Composabe Overlays☆73Updated last year
- This XUP course provides an introduction to embedded system design on Zynq using the Xilinx Vivado software suite.☆86Updated 2 years ago
- RISC-V Integration for PYNQ☆177Updated 6 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆80Updated 3 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆65Updated last year
- RTL Verilog library for various DSP modules☆91Updated 3 years ago
- A PYNQ overlay demonstrating Pythonic DSP running on Zynq UltraScale+☆40Updated 3 years ago
- An implementation of the CORDIC algorithm in Verilog.☆102Updated 6 years ago
- This is a simple project that shows how to multiply two 3x3 matrixes in Verilog.☆53Updated 8 years ago
- Verilog digital signal processing components☆158Updated 3 years ago
- Vitis Model Composer Examples and Tutorials☆108Updated last week
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆96Updated last week
- PYNQ support and examples for Kria SOMs☆117Updated last year
- A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.☆68Updated last year
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆79Updated 4 years ago
- Fixed Point Math Library for Verilog☆143Updated 11 years ago
- Verilog RTL Design☆45Updated 4 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆48Updated last year
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆31Updated 5 years ago
- 16-bit Adder Multiplier hardware on Digilent Basys 3☆81Updated 2 years ago
- IP operations in verilog (simulation and implementation on ice40)☆61Updated 6 years ago
- EE 260 Winter 2017: Advanced VLSI Design☆66Updated 8 years ago
- ☆98Updated last year
- SystemVerilog HDL and TB code Deep Neural Network Hardware Accelerator implementation on zybo 7010 FPGA and also C code for Vivado SDK So…☆112Updated 5 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆73Updated 10 months ago
- A Tutorial on Putting High-Level Synthesis cores in PYNQ☆107Updated 7 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆67Updated 3 years ago
- This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite☆103Updated 6 years ago
- ☆42Updated last year