ymanerka / ccicheck
☆9Updated 9 years ago
Alternatives and similar repositories for ccicheck:
Users that are interested in ccicheck are comparing it to the libraries listed below
- RTLCheck☆21Updated 6 years ago
- A tutorial for setting up Symbolic Quick Error Detection (SQED) using the model checker, CoSA, on the Ride Core☆12Updated 5 years ago
- Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…☆17Updated 5 months ago
- ☆18Updated 9 months ago
- ☆12Updated 10 months ago
- ☆11Updated last year
- COATCheck☆13Updated 6 years ago
- ☆19Updated 10 years ago
- ☆13Updated 4 years ago
- A Coq framework to support structural design and proof of hardware cache-coherence protocols☆13Updated 2 years ago
- ILA Model Database☆22Updated 4 years ago
- This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…☆17Updated 2 years ago
- ☆12Updated 4 years ago
- ☆11Updated 3 years ago
- Memory consistency model checking and test generation library.☆15Updated 8 years ago
- ☆17Updated 10 months ago
- A Modular Open-Source Hardware Fuzzing Framework☆32Updated 3 years ago
- Collection for submission (Hardware Model Checking Benchmark)☆9Updated 6 months ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- PipeProof☆11Updated 5 years ago
- PyCaliper is Python-based tooling infrastructure that allows the verification and synthesis of specifications (properties) for RTL (e.g.,…☆20Updated 3 months ago
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆24Updated 6 months ago
- Project Repo for the Simulator Independent Coverage Research☆18Updated 2 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 4 years ago
- Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…☆12Updated last month
- Random Generator of Btor2 Files☆10Updated last year
- Fast Symbolic Repair of Hardware Design Code☆22Updated 3 months ago
- RISC-V Formal in Chisel☆11Updated last year
- A synthesis flow for hybrid processing-in-RRAM modes☆12Updated 3 years ago
- ANSI-C benchmarks generated from Verilog RTL circuits with safety assertions. Used for Formal Property Verification.☆14Updated 6 years ago