Alternatives and similar repositories for ot-sca

Users that are interested in ot-sca are comparing it to the libraries listed below

• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆23Updated last year
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆118Updated this week
• antmicro / rowhammer-tester
  ☆71Updated 2 weeks ago
• agra-uni-bremen / symex-vp
  A concolic testing engine for RISC-V embedded software with support for SystemC peripherals
  ☆26Updated 2 years ago
• zero-day-labs / riscv-iopmp
  IOPMP IP
  ☆21Updated 4 months ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆59Updated this week
• epfl-vlsc / bitfiltrator
  Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats
  ☆48Updated 2 years ago
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 4 years ago
• socsecresearch / SoC_Vulnerability_Benchmarks
  ☆11Updated 7 months ago
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 5 years ago
• vmarribas / VerMFi
  VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …
  ☆20Updated 6 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆73Updated 3 weeks ago
• openhwgroup / cva6-platform
  CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
  ☆12Updated 2 years ago
• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 5 years ago
• westerndigitalcorporation / swerv_eh1_fpga
  FPGA reference design for the the Swerv EH1 Core
  ☆72Updated 5 years ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• fatestudio / RSA4096
  4096bit RSA project, with verilog code, python test code, etc
  ☆47Updated 6 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• zero-day-labs / riscv-iommu-demo
  RISC-V IOMMU Demo (Linux & Bao)
  ☆23Updated 2 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆66Updated 3 years ago
• intel / pfr-wilson-city
  ☆24Updated 2 months ago
• newaetech / CW305-Arm-DesignStart
  Instruction and files for porting Arm DesignStart to CW305.
  ☆14Updated 2 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆29Updated 2 months ago
• BLu85 / AES-GCM-128-192-256-bits
  Configurable AES-GCM IP (128, 192, 256 bits)
  ☆39Updated 3 months ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆40Updated 3 weeks ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 8 years ago
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆36Updated 4 years ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆82Updated last month
• secworks / trng
  True Random Number Generator core implemented in Verilog.
  ☆78Updated 5 years ago