Alternatives and similar repositories for A2

Users that are interested in A2 are comparing it to the libraries listed below

• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆25Updated 8 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆15Updated 3 years ago
• compsec-snu / specdoctor
  ☆25Updated 2 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 6 years ago
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆64Updated 5 years ago
• gatelabdavis / SMTAttack
  SMT Attack
  ☆21Updated 4 years ago
• RPTU-EIS / upec-boom-verification-suite
  This repository contains the verification suite for verifying Berkeley Out-of-Order Machine (BOOM) against transient execution attacks ba…
  ☆17Updated 2 years ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆22Updated 8 months ago
• daniellustig / coatcheck
  COATCheck
  ☆13Updated 6 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆23Updated 4 years ago
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆60Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆21Updated 3 months ago
• comsec-group / mucfi
  Microarchitectural control flow integrity (𝜇CFI) verification checks whether there exists a control or data flow from instruction's ope…
  ☆12Updated 2 months ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆66Updated 11 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆37Updated this week
• cwfletcher / stt
  ☆35Updated 4 years ago
• hackdac / hackdac_2018_beta
  The SoC used for the beta phase of Hack@DAC 2018.
  ☆17Updated 5 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆67Updated 2 months ago
• aakahlow / gem5Valid_Haswell
  ☆19Updated 5 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆53Updated last month
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆93Updated this week
• ekiwi / rtl-fuzz-lab
  A Modular Open-Source Hardware Fuzzing Framework
  ☆33Updated 3 years ago
• CSL-KU / SpectreGuard
  Data-centric defense mechanism against Spectre attacks. (DAC'19)
  ☆11Updated 5 years ago
• daniellustig / pipecheck
  ☆19Updated 10 years ago
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆32Updated last month
• zzyppo / tagged_security_riscv
  Implementation of Tagged Memory security policies into Rocket Core
  ☆10Updated 8 years ago
• ymanerka / ccicheck
  ☆9Updated 9 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆17Updated 7 months ago
• googleinterns / hw-fuzzing
  ☆83Updated 2 years ago