impedimentToProgress / A2Links
☆14Updated 7 years ago
Alternatives and similar repositories for A2
Users that are interested in A2 are comparing it to the libraries listed below
Sorting:
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆26Updated 2 months ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆64Updated 5 years ago
- Security Test Benchmark for Computer Architectures☆21Updated 6 months ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆22Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆60Updated 5 years ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆109Updated 3 years ago
- ☆87Updated 2 years ago
- COATCheck☆13Updated 6 years ago
- ☆35Updated 4 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- SMT Attack☆21Updated 4 years ago
- CleanupSpec (MICRO-2019)☆16Updated 4 years ago
- ☆25Updated 2 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 11 months ago
- The SoC used for the beta phase of Hack@DAC 2018.☆17Updated 5 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆16Updated 4 years ago
- A Modeling and Verification Platform for SoCs using ILAs☆77Updated last year
- New Cache implementation using Gem5☆13Updated 11 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆34Updated 3 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆69Updated 5 months ago
- All the tools you need to reproduce the CellIFT paper experiments☆21Updated 6 months ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆137Updated 2 years ago
- Implementation of Tagged Memory security policies into Rocket Core☆10Updated 8 years ago
- ☆93Updated last year
- ☆16Updated 4 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆65Updated 2 years ago
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 5 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆54Updated 6 years ago
- ☆19Updated 5 months ago