impedimentToProgress / A2Links
☆14Updated 8 years ago
Alternatives and similar repositories for A2
Users that are interested in A2 are comparing it to the libraries listed below
Sorting:
- A behavioural cache model for analysing the cache behaviour under side-channel attack.☆28Updated 7 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆68Updated 6 years ago
- A port of the RIPE suite to RISC-V.☆29Updated 7 years ago
- COATCheck☆13Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆24Updated last year
- ☆25Updated 2 years ago
- Security Test Benchmark for Computer Architectures☆21Updated 4 months ago
- Testing processors with Random Instruction Generation☆50Updated 2 weeks ago
- CleanupSpec (MICRO-2019)☆16Updated 5 years ago
- Code repository for Coppelia tool☆23Updated 5 years ago
- This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.☆57Updated 6 years ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆112Updated 3 years ago
- SoftMC is an experimental FPGA-based memory controller design that can be used to develop tests for DDR3 SODIMMs using a C++ based API. T…☆143Updated 2 years ago
- ☆34Updated last month
- Data-centric defense mechanism against Spectre attacks. (DAC'19)☆11Updated 6 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆23Updated 3 years ago
- Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.☆61Updated 5 years ago
- A Modular Open-Source Hardware Fuzzing Framework☆36Updated 4 years ago
- ☆87Updated 3 years ago
- ☆36Updated 6 years ago
- SMT Attack☆22Updated 4 years ago
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆17Updated 4 years ago
- Implementation of Tagged Memory security policies into Rocket Core☆10Updated 9 years ago
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…☆67Updated 3 years ago
- A Coherent Multiprocessor Cache Simulator Based on the SuperESCalar Cache Model☆28Updated 12 years ago
- PipeProof☆11Updated 6 years ago
- The SoC used for the beta phase of Hack@DAC 2018.☆18Updated 5 years ago
- ☆27Updated 10 months ago
- ☆19Updated 5 years ago
- ☆14Updated 4 years ago