Alternatives and similar repositories for CacheFX:

Users that are interested in CacheFX are comparing it to the libraries listed below

• 0xADE1A1DE / BunnyHop
  PoC for Paper: BunnyHop Exploiting the Instruction Prefetcher (USENIX Security 2023)
  ☆12Updated last year
• flowyroll / medusa
  Medusa Repository: Transynther tool and Medusa Attack
  ☆21Updated 4 years ago
• libtea / frameworks
  Microarchitectural attack development frameworks for prototyping attacks in native code (C, C++, ASM) and in the browser
  ☆61Updated 2 years ago
• cwfletcher / oisa
  Data oblivious ISA prototyped on the RISC-V BOOM processor.
  ☆20Updated 2 years ago
• proteus-core / prospect
  ProSpeCT: Provably Secure Speculation for the Constant-Time Policy.
  ☆15Updated 4 months ago
• gururaj-s / mirage
  MIRAGE (USENIX Security 2021)
  ☆12Updated last year
• vusec / tlbkit
  some tlb experimentation code: calculate L1, L2 miss penalties and show cross-HT interference.
  ☆13Updated 5 years ago
• cgvwzq / cachequery
  HW interface for memory caches
  ☆26Updated 4 years ago
• gururaj-s / streamline
  Streamline Covert Channel Attack (presented in ASPLOS'21)
  ☆19Updated 4 years ago
• facebookresearch / AutoCAT
  AutoCAT: Reinforcement Learning for Automated Exploration of Cache-Timing Attacks
  ☆44Updated last year
• amdprefetch / amd-prefetch-attacks
  ☆23Updated last year
• compsec-snu / specdoctor
  ☆23Updated 2 years ago
• flowyroll / uarchsec
  ☆44Updated 6 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆60Updated 7 months ago
• comparch-security / cache-model
  A behavioural cache model for analysing the cache behaviour under side-channel attack.
  ☆22Updated 5 months ago
• CTSRD-CHERI / Test-Suite-Transient-Execution
  Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly
  ☆13Updated 3 years ago
• ECLab-ITU / Cache-Side-Channel-Attacks
  This repository contains source code and experimental data of multiple cache side-channel attacks on Intel x86 architecture.
  ☆48Updated 5 years ago
• greenlsi / reload_refresh
  Reload+Refresh PoC
  ☆14Updated 5 years ago
• comparch-security / cpu-sec-bench
  Security Test Benchmark for Computer Architectures
  ☆20Updated last week
• mjyan0720 / InvisiSpec-1.0
  Gem5 implementation of "InvisiSpec", a defense mechanism of speculative execution attacks on cache hierarchy.
  ☆59Updated 4 years ago
• gururaj-s / cleanupspec
  CleanupSpec (MICRO-2019)
  ☆17Updated 4 years ago
• googleinterns / hw-fuzzing
  ☆80Updated 2 years ago
• vusec / tlbdr
  ☆18Updated 2 years ago
• hw-sw-contracts / revizor
  Fuzzer that searches for vulnerabilities like Spectre and Meltdown in CPUs
  ☆42Updated 2 years ago
• CMU-SAFARI / BEER
  BEER determines an ECC code's parity-check matrix based on the uncorrectable errors it can cause. BEER targets Hamming codes that are use…
  ☆19Updated 4 years ago
• cispa / mwait
  Proof-of-concept implementation for the paper "(M)WAIT for It: Bridging the Gap between Microarchitectural and Architectural Side Channel…
  ☆25Updated last year
• nepoche / Flush-Reload
  A flush-reload side channel attack implementation
  ☆44Updated 2 years ago
• Secure-AI-Systems-Group / Mastik
  GitHub (mirror) repository for the Mastik toolkit, written by Yuval Yarom https://cs.adelaide.edu.au/~yval/Mastik/
  ☆37Updated 5 years ago
• rzhang2285 / Coppelia
  Code repository for Coppelia tool
  ☆22Updated 4 years ago