acmert / kyber-polmul-hw
Hardware implementation of polynomial multiplication operation of CRYSTALS-KYBER PQC scheme
☆21Updated 2 years ago
Related projects: ⓘ
- High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.☆39Updated last year
- ☆41Updated 3 years ago
- ☆15Updated 2 years ago
- processor for post-quantum cryptography☆14Updated 4 years ago
- ☆22Updated last month
- ☆11Updated 2 weeks ago
- ☆14Updated 2 months ago
- ☆19Updated 3 years ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 6 months ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆36Updated 7 years ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆20Updated last week
- Hardware implementation of Saber☆6Updated 4 years ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 9 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆11Updated 5 years ago
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆39Updated 3 months ago
- Description of Chinese SM3 Hash algorithm with Verilog HDL☆45Updated 6 years ago
- Acceleration of TFHE-based Homomorphic NAND Gate on FPGA☆13Updated 3 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 6 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆25Updated 6 months ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- ☆20Updated 5 years ago
- Implementation of Number-theoretic transform(NTT) algorithm on FPGA; 快速数论变换(NTT)的FPGA实现,基为2,有两个并行的蝶形单元☆12Updated 2 years ago
- CVA6 SDK containing RISC-V tools and Buildroot☆59Updated 2 months ago
- ☆20Updated last year
- Defense/Attack PUF Library (DA PUF Library)☆45Updated 4 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago
- HW Design Collateral for Caliptra RoT IP☆65Updated this week
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 3 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆20Updated 6 years ago
- David Canright's tiny AES S-boxes☆20Updated 10 years ago