Alternatives and similar repositories for riskow:

Users that are interested in riskow are comparing it to the libraries listed below

• RISCuinho / core
  **RISC**uinho - A scratch in the possibilities in the universe of microcontrollers
  ☆21Updated 2 years ago
• racerxdl / riscv-emulator
  Golang RISC-V emulator that can play DOOM
  ☆68Updated last year
• racerxdl / biggateboy
  WIP Big FPGA Gameboy
  ☆21Updated 3 years ago
• zxmarcos / riscado-v
  RISCV implementation in Verilog (RV32I spec)
  ☆17Updated 4 years ago
• racerxdl / asm2web
  Código usado na live de Assembly for Noobs!
  ☆57Updated 4 years ago
• riscv-steel / riscv-steel
  RISC-V 32-bit microcontroller developed in Verilog
  ☆167Updated 4 months ago
• zxmarcos / huedeon-gpu
  FPGA GPU design for DE1-SoC
  ☆73Updated 3 years ago
• JN513 / Risco-5
  Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
  ☆18Updated 3 months ago
• racerxdl / pcieledblink
  Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)
  ☆21Updated 3 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆58Updated 2 months ago
• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆80Updated last year
• simoesusp / Processador-ICMC
  Development of a complete environment to teach and learn computer architecture, VHDL processor design and Assembly language
  ☆73Updated 8 months ago
• stnolting / neorv32-verilog
  ♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.
  ☆73Updated this week
• SonalPinto / kronos
  Kronos is a 3-stage in-order RISC-V RV32I_Zicsr_Zifencei core geared towards FPGA implementations
  ☆70Updated last year
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆226Updated 3 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆63Updated this week
• racerxdl / goboy
  Playing GameBoy Emulation in GoLang (ported from https://github.com/racerxdl/GameBoyEmulator)
  ☆41Updated 3 years ago
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆243Updated 3 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆165Updated 4 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆50Updated last year
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆284Updated last week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆172Updated last year
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆142Updated 3 months ago
• racerxdl / esp32-rjtag
  ESP32 Remote JTAG Host for programming FPGAs
  ☆26Updated 4 years ago
• RodrigoDornelles / 3bc-lang
  Low-level language, tiny virtual machine, minimal runtime, intermediate representation, embeddable, easy for beginners. (Friendly Punched…
  ☆245Updated 9 months ago
• carlosedp / chiselv
  A RISC-V Core (RV32I) written in Chisel HDL
  ☆101Updated 8 months ago
• sjohann81 / hf-risc
  HF-RISC SoC
  ☆30Updated 3 months ago
• olofk / corescore
  CoreScore
  ☆143Updated 3 weeks ago
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆69Updated 5 years ago