Controller module for RISC-V core CI/CD
☆17May 23, 2025Updated last year
Alternatives and similar repositories for processor-ci-controller
Users that are interested in processor-ci-controller are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Apr 16, 2026Updated 2 months ago
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆18Oct 29, 2024Updated last year
- A small and simple rv32i core written in Verilog☆18Jul 29, 2022Updated 3 years ago
- Browser extension that adds a new search keyword for more easily navigating to Lemmy communities.☆11Jul 13, 2023Updated 2 years ago
- Project 2.2 Frequency counter☆12May 30, 2025Updated last year
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- M-extension for RISC-V cores.☆32Nov 21, 2024Updated last year
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- 2D physics engine for games.☆21Jun 16, 2026Updated 2 weeks ago
- Approximate arithmetic circuits for FPGAs☆13Feb 19, 2020Updated 6 years ago
- The missing part of your WM, a customizable battery notifier for Linux (?Lightweight battery daemon)☆24Jun 13, 2026Updated 2 weeks ago
- A privacy-focused voice communication server and client, inspired by TeamSpeak, built entirely in Go.☆113May 24, 2026Updated last month
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆15Jan 9, 2017Updated 9 years ago
- RISCV implementation in Verilog (RV32I spec)☆18Nov 5, 2025Updated 7 months ago
- End-to-end encrypted email - Proton Mail • AdSpecial offer: 40% Off Yearly / 80% Off First Month. All Proton services are open source and independently audited for security.
- A simple particle simulation made with python and pygame.☆13Jan 21, 2021Updated 5 years ago
- RISC-V processor model☆11Nov 10, 2020Updated 5 years ago
- Implementation of Partially Parellel LDPC Code Decoder in Verilog☆15Jul 23, 2020Updated 5 years ago
- HDMI + GPU-pipeline + FFT☆14Mar 4, 2016Updated 10 years ago
- Convert Verilog to a Hardcaml design☆22May 18, 2026Updated last month
- Verilog Model for W25Q128JVxIM Serial Flash Memory☆18Jun 7, 2020Updated 6 years ago
- A harvard architecture CPU based on RISC-V.☆16Aug 25, 2023Updated 2 years ago
- Linux 4 for Caninos Labrador V3☆14Sep 25, 2023Updated 2 years ago
- Análise do Aplicativo Prévias PSDB 2021☆18Nov 23, 2021Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- NSCSCC “龙芯杯” 2024 个人赛 LoongArch 赛道三等奖☆19Aug 17, 2024Updated last year
- Submission template for Tiny Tapeout 8 - Verilog HDL Projects☆18Jul 12, 2024Updated last year
- An open source SDR SDRAM controller based on the AXI4 bus and verified by FPGA and tapeout. It can support memory particles of different …☆22May 12, 2025Updated last year
- ☆21Mar 25, 2024Updated 2 years ago
- Build scripts of ci.rvperf.org☆12Apr 10, 2026Updated 2 months ago
- A Verilog parser for Haskell.☆37Jul 6, 2021Updated 4 years ago
- 16QAM modulation and demodulation by Verilog☆21Jan 4, 2021Updated 5 years ago
- An FPGA-based RISC-V CPU☆16Dec 7, 2021Updated 4 years ago
- Submission template for Tiny Tapeout 7 - Verilog HDL Projects☆22May 30, 2024Updated 2 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- OpenMP vs Offload☆24Jun 2, 2023Updated 3 years ago
- A pipelined brainfuck softcore in Verilog☆20Aug 5, 2014Updated 11 years ago
- Open-source PDK version manager☆53Jun 15, 2026Updated 2 weeks ago
- Bitstream to Verilog decompiler for Lattice FPGA ECP5 chip.☆23Oct 10, 2021Updated 4 years ago
- HDL code for a complex multiplier with AXI stream interface☆17Mar 18, 2026Updated 3 months ago
- Final Project for my course in Advanced Verification with SystemVerilog OOP☆22Dec 17, 2021Updated 4 years ago
- A customized RISCV core made using verilog☆18Mar 4, 2021Updated 5 years ago