LSC-Unicamp / processor-ci-controllerLinks
Controller module for RISC-V core CI/CD
☆17Updated 8 months ago
Alternatives and similar repositories for processor-ci-controller
Users that are interested in processor-ci-controller are comparing it to the libraries listed below
Sorting:
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆12Updated 2 years ago
- wifi☆12Updated 8 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆11Updated last year
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Updated 5 years ago
- A python project to automatically generate the UVM testbench document.☆21Updated last year
- Digital IC design and vlsi notes☆12Updated 5 years ago
- Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators☆11Updated 2 years ago
- A Barrel design of RV32I☆22Updated 2 years ago
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 8 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Updated 6 years ago
- VCD visualizer: view your waveforms in ASCII format, or export them to TikZ figures.☆32Updated 3 months ago
- 32-bit soft RISCV processor for FPGA applications☆19Updated 2 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆34Updated last month
- Simple RiscV core for academic purpose.☆23Updated 5 years ago
- picorv32_soc, simulation env, FPGA, boot code, RTOS☆16Updated 7 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆21Updated 5 years ago
- Hardware implementation of HDR image producing algorithm☆16Updated 3 years ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆21Updated 2 years ago
- 关于数字IC的笔试面试题☆14Updated 6 years ago
- Mirror of tachyon-da cvc Verilog simulator☆48Updated 2 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- Python Utilities to use Xilinx Vivado Tools from Python Scripts☆22Updated 5 years ago
- ☆15Updated last year
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Updated 4 years ago
- ☆20Updated 3 years ago
- Go Board FPGA Project for Ambient Light Sensor in VHDL and Verilog☆10Updated 6 years ago
- UVM/systemverilog/verilog/python VIM IDE☆16Updated 12 years ago
- A current mode buck converter on the SKY130 PDK☆34Updated 4 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 8 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago