LSC-Unicamp / processor-ci-controllerLinks
Controller module for RISC-V core CI/CD
☆17Updated 5 months ago
Alternatives and similar repositories for processor-ci-controller
Users that are interested in processor-ci-controller are comparing it to the libraries listed below
Sorting:
- wifi☆12Updated 8 years ago
- This repo is to inplemente the riscv soc on the xilinx pynq-z2 board☆11Updated last year
- A python project to automatically generate the UVM testbench document.☆21Updated last year
- Digital IC design and vlsi notes☆12Updated 5 years ago
- Porting FreeRTOS to a RISC-V based system on PYNQ-Z2☆10Updated 10 months ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车,分为两个部分,控制器部分和小车部分,通过蓝牙信号进行连接。 控制部分可以通过 加速度传感器检测手势,从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆14Updated 6 years ago
- Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators☆11Updated last year
- HW and SW based implementation of Canny Edge Detection Algorithm.☆12Updated 7 years ago
- In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…☆19Updated 5 years ago
- 关于数字IC的笔试面试题☆13Updated 5 years ago
- Systemverilog DPI-C call Python function☆26Updated 4 years ago
- Chips 2.0 Demo for Atlys Spartan 6 development platform. Web app using C to Verilog TCP/IP server.☆16Updated 7 years ago
- Sobel is first order or gradient based edge operator for images and it is implemented using verilog.☆14Updated 4 years ago
- Hardware implementation of HDR image producing algorithm☆16Updated 3 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆31Updated 5 months ago
- Test dashboard for verification features in Verilator☆27Updated last week
- picorv32_soc, simulation env, FPGA, boot code, RTOS☆15Updated 7 years ago
- This project aims to design an 32-point FFT (Fast Fourier Transform) based DIT (decimation in time) Butterfly Algorithm with multiple clo…☆56Updated 2 years ago
- UVM/systemverilog/verilog/python VIM IDE☆16Updated 12 years ago
- Updated Xilinx PYNQ for Zynq + ZynqMP python HW acceleration development☆12Updated 7 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Updated 4 years ago
- 32 Bit RippleCarry, CarrySkip, CarrySelect, CarryIncrement, Sklansky, Brent-Kung, Kogge-Stone and CarryLookahead adders with their intern…☆25Updated 7 years ago
- UVM resource from github, run simulation use YASAsim flow☆30Updated 5 years ago
- 数字IC验证案例(SV and UVM)☆26Updated 4 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆49Updated 3 years ago
- Implementing Different Adder Structures in Verilog☆75Updated 6 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…☆17Updated 5 years ago
- 32-bit soft RISCV processor for FPGA applications☆17Updated last year
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆35Updated 8 months ago
- Python Tool for UVM Testbench Generation☆54Updated last year