Alternatives and similar repositories for processor-ci-controller:

Users that are interested in processor-ci-controller are comparing it to the libraries listed below

• ShaheerSajid / RISCV
  32-bit soft RISCV processor for FPGA applications
  ☆15Updated last year
• riscv-verification / riscvISACOV
  SystemVerilog Functional Coverage for RISC-V ISA
  ☆26Updated 6 months ago
• JN513 / Risco-5
  Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
  ☆18Updated 5 months ago
• AUCOHL / Lighter
  An automatic clock gating utility
  ☆45Updated 8 months ago
• armleo / ArmleoCPU
  ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set
  ☆6Updated 2 years ago
• bespoke-silicon-group / bsg_sv2v
  A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.
  ☆40Updated last year
• Ben1152000 / sootty
  A command-line tool for displaying vcd waveforms.
  ☆53Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• pulp-platform / occamy
  A high-efficiency system-on-chip for floating-point compute workloads.
  ☆29Updated 2 months ago
• pulp-platform / tech_cells_generic
  Technology dependent cells instantiated in the design for generic process (simulation, FPGA)
  ☆48Updated 2 months ago
• efabless / sky130_sram_macros_old
  ☆36Updated 2 years ago
• cambridgehackers / open-src-cvc
  Mirror of tachyon-da cvc Verilog simulator
  ☆42Updated last year
• b224hisl / rioschip
  ☆33Updated 2 years ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆76Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• shalan / Awesome-Sky130-IPs
  ☆10Updated last year
• vmunoz82 / sudoku-challenge
  Solving Sudokus using open source formal verification tools
  ☆16Updated 2 years ago
• chipsalliance / verible-linter-action
  Automatic SystemVerilog linting in github actions with the help of Verible
  ☆33Updated 5 months ago
• The-OpenROAD-Project / megaboom
  ☆25Updated 2 weeks ago
• hdl / containers
  Building and deploying container images for open source electronic design automation (EDA)
  ☆112Updated 6 months ago
• chili-chips-ba / openCologne
  Spicing up the first and (no longer) the only EU FPGA chip with a flashy new board, loaded with a suite of engaging demos and examples =>…
  ☆61Updated last week
• dpretet / bster
  Implementation of a binary search tree algorithm in a FPGA/ASIC IP
  ☆19Updated 3 years ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated 11 months ago
• StanfordVLSI / DaVE
  tools regarding on analog modeling, validation, and generation
  ☆22Updated last year
• povik / yosys-slang
  SystemVerilog frontend for Yosys
  ☆81Updated 2 weeks ago
• sjohann81 / hf-risc
  HF-RISC SoC
  ☆31Updated 4 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• yuyuranium / RTOS-Project-2023-riscv-freertos-on-pynq
  Porting FreeRTOS to a RISC-V based system on PYNQ-Z2
  ☆10Updated 3 months ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆11Updated last year