LSC-Unicamp / processor-ci-controller
Controller module for RISC-V core CI/CD
☆16Updated 3 weeks ago
Alternatives and similar repositories for processor-ci-controller
Users that are interested in processor-ci-controller are comparing it to the libraries listed below
Sorting:
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆16Updated 4 years ago
- CMake based hardware build system☆18Updated this week
- Open source designs developed with IHP 130nm BiCMOS Open Source PDK. Documentation at https://ihp-open-ip.readthedocs.io/en/latest/☆47Updated last month
- A command-line tool for displaying vcd waveforms.☆56Updated last year
- ☆25Updated this week
- ☆39Updated 2 months ago
- Solving Sudokus using open source formal verification tools☆16Updated 2 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆41Updated 2 years ago
- ☆36Updated 2 years ago
- Plugins for Yosys developed as part of the F4PGA project.☆83Updated 11 months ago
- SystemVerilog Functional Coverage for RISC-V ISA☆28Updated 7 months ago
- RPHAX provides a quick automation flow to develop and prototype hardware accelerators on Xilinx FPGAs. Currently, the framework has suppo…☆18Updated 2 years ago
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆18Updated 6 months ago
- M-extension for RISC-V cores.☆30Updated 5 months ago
- An automatic clock gating utility☆47Updated 3 weeks ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆42Updated 3 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated last year
- Characterizer☆22Updated 8 months ago
- Open Source AES☆31Updated last year
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- ☆46Updated 3 months ago
- OSVVM Documentation☆33Updated last week
- ☆10Updated last year
- Library of open source Process Design Kits (PDKs)☆40Updated last week
- SystemVerilog RTL Linter for YoSys☆20Updated 5 months ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆44Updated 3 years ago
- A tool for synthesizing Verilog programs☆78Updated this week
- A current mode buck converter on the SKY130 PDK☆27Updated 3 years ago
- This project presents a 10Gb/s transceiver design using 65nm CMOS process, based on a 10GBASE-KR standard.☆23Updated 6 years ago