Alternatives and similar repositories for processor-ci-website

Users that are interested in processor-ci-website are comparing it to the libraries listed below

• JN513 / Risco-5
  Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.
  ☆17Updated last year
• racerxdl / riskow
  Learning how to make a RISC-V
  ☆135Updated 4 years ago
• jeceljr / LivroComputadoresEVideogames
  Material do Livro "Computadores E Videogames"
  ☆16Updated 2 weeks ago
• RISCuinho / core
  **RISC**uinho - A scratch in the possibilities in the universe of microcontrollers
  ☆23Updated 3 years ago
• Astrocoders / pix-dict-quickstart
  Quickstart da API do DICT feito em Reason nativo
  ☆13Updated 5 years ago
• Astrocoders / pix-dashboard
  PIX dashboard
  ☆13Updated 2 years ago
• pulp-platform / bender
  A dependency management tool for hardware projects.
  ☆335Updated this week
• openhwgroup / programs
  Documentation for the OpenHW Group's set of CORE-V RISC-V cores
  ☆219Updated last week
• LSC-Unicamp / processor-ci-controller
  Controller module for RISC-V core CI/CD
  ☆17Updated 6 months ago
• chipsalliance / Cores-VeeR-EL2
  VeeR EL2 Core
  ☆303Updated this week
• PrincetonUniversity / prga
  Open-source FPGA research and prototyping framework.
  ☆210Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆126Updated last month
• racerxdl / DOS
  D Operating System - Just because HUEBR
  ☆13Updated 5 years ago
• rafaelcalcada / rvx
  RISC-V soft-core microcontroller for FPGA implementation
  ☆187Updated last month
• sibelius / reactconf-taming-data-fetching
  Taming Data Fetching: From pure React hooks to Relay Modern and Suspense (ReactConfBR19)
  ☆18Updated 6 years ago
• simoesusp / Processador-ICMC
  Development of a complete environment to teach and learn computer architecture, VHDL processor design and Assembly language
  ☆83Updated 2 months ago
• BSVLang / Main
  Main page
  ☆128Updated 5 years ago
• Astrocoders / bs-react-native-vector-icons
  ReasonML bindings for react-native-vector-icons
  ☆16Updated 2 years ago
• chipsalliance / VeeRwolf
  FuseSoC-based SoC for VeeR EH1 and EL2
  ☆331Updated 11 months ago
• marlls1989 / pulsar
  Pulsar asynchronous synthesis framework
  ☆13Updated 4 years ago
• fakenickels / es2077-course-slides
  Slides e materiais
  ☆29Updated 2 years ago
• tenstorrent / riescue
  RISC-V Directed Test Framework and Compliance Suite, RiESCUE
  ☆38Updated this week
• openhwgroup / core-v-mcu
  This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.
  ☆187Updated last month
• quan-to / quanto-commons
  Common Node things made by QUANTO
  ☆18Updated 2 years ago
• fakenickels / es2077-reactconf
  ES2077 is ReasonML
  ☆32Updated 5 years ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆158Updated 8 months ago
• open-banking-brasil / docs
  ☆31Updated 5 years ago
• bespoke-silicon-group / bsg_manycore
  Tile based architecture designed for computing efficiency, scalability and generality
  ☆274Updated last month
• chipsalliance / synlig
  SystemVerilog synthesis tool
  ☆218Updated 8 months ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆88Updated last month