LSC-Unicamp / processor-ci-website
Processor CI project Website
☆10Updated 3 weeks ago
Alternatives and similar repositories for processor-ci-website
Users that are interested in processor-ci-website are comparing it to the libraries listed below
Sorting:
- Multi-cycle RISC-V processor with RV32I/E[M] implementation, built during a few days off.☆18Updated 6 months ago
- Controller module for RISC-V core CI/CD☆16Updated 3 weeks ago
- Learning how to make a RISC-V☆136Updated 4 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆91Updated 2 weeks ago
- Material do Livro "Computadores E Videogames"☆13Updated 7 months ago
- D Operating System - Just because HUEBR☆13Updated 4 years ago
- RISC-V microcontroller IP core developed in Verilog☆175Updated last month
- A dependency management tool for hardware projects.☆297Updated this week
- SystemVerilog synthesis tool☆190Updated 2 months ago
- Development of a complete environment to teach and learn computer architecture, VHDL processor design and Assembly language☆74Updated 11 months ago
- WIP Big FPGA Gameboy☆21Updated 4 years ago
- Verilog Configurable Cache☆178Updated 5 months ago
- The next generation of OpenLane, rewritten from scratch with a modular architecture☆284Updated 2 months ago
- RISC-V Formal Verification Framework☆137Updated this week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆72Updated 8 months ago
- Open-source FPGA research and prototyping framework.☆205Updated 9 months ago
- Documentation for the OpenHW Group's set of CORE-V RISC-V cores☆211Updated last month
- Stratix V PCIe Ledblink (for usage in Microsoft Storey Peak boards)☆22Updated 3 years ago
- Universal Hardware Data Model. A complete modeling of the IEEE SystemVerilog Object Model with VPI Interface, Elaborator, Serialization, …☆218Updated this week
- This is the CORE-V MCU project, hosting CORE-V's embedded-class cores.☆174Updated last week
- ☆52Updated 2 months ago
- VeeR EL2 Core☆275Updated 2 weeks ago
- Test suite designed to check compliance with the SystemVerilog standard.☆318Updated this week
- A tool for synthesizing Verilog programs☆78Updated this week
- Código usado na live de Assembly for Noobs!☆57Updated 4 years ago
- App de persistência para fins didáticos☆12Updated 7 years ago
- Verilog module for I2C Master, up to 16 bit sub addr, 7bit slave address, and multiple byte read/write capable☆18Updated 5 years ago
- Main page☆126Updated 5 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆166Updated 5 months ago
- Waveform Viewer Extension for VScode☆170Updated this week