☆25Mar 19, 2026Updated 6 months ago
Alternatives and similar repositories for eda-sim
Users that are interested in eda-sim are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆63May 22, 2026Updated 4 months ago
- non-local means filter for OpenCV☆13Jul 6, 2013Updated 13 years ago
- ☆15Aug 1, 2023Updated 3 years ago
- verilog实现CLAHE（限制对比度自适应直方图均衡化）算法，并进行资源优化，含vivado综合工程。 // Verilog implementation of CLAHE (Contrast Limited Adaptive Histogram…☆21Apr 30, 2026Updated 5 months ago
- Open-source, evidence-driven MCP server for RTL simulation debugging: correlate VCS/Xcelium logs, VCD/FSDB waveforms, SystemVerilog/UVM s…☆118Updated this week
- End-to-end encrypted cloud storage - Proton Drive • AdSpecial offer: 40% Off Yearly / 80% Off First Month. Protect your most important files, photos, and documents from prying eyes.
- Functional Verification of Physical Layer of PCI Express Gen5.0 Graduation Project Using UVM☆36Jul 17, 2025Updated last year
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago
- ☆28Sep 19, 2026Updated 3 weeks ago
- PTPv2 hardware engine design for 10G Ethernet, described in Verilog HDL☆19May 27, 2025Updated last year
- Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP sp…☆24Jul 14, 2026Updated 2 months ago
- Extending BookSim2.0 and HotSpot6.0 for Power, Performance and Thermal evaluation of 3D NoC Architectures☆14Aug 9, 2019Updated 7 years ago
- A collection of examples showcasing PyCDE and Mini RISC-V implementation.☆10Jul 23, 2026Updated 2 months ago
- This script builds the UVM register model, based on pre-defined address map in markdown (mk) style☆12Mar 23, 2018Updated 8 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- UVM Clock and Reset Agent☆15Jun 29, 2017Updated 9 years ago
- Implementation of the PCIe physical layer☆64Jul 11, 2025Updated last year
- Various low power labs using sky130☆13Sep 3, 2021Updated 5 years ago
- ☆15Jun 27, 2024Updated 2 years ago
- UVM testbench for verifying the Pulpino SoC☆14Mar 23, 2020Updated 6 years ago
- Backup: Library implementing a C TLM-2 style to bridge C models to SystemC TLM-2.0 (C++) from GreenSocs (https://git.greensocs.com/tlm/tl…☆20Aug 13, 2018Updated 8 years ago
- Final project for Computer Architecture FA16☆20Jan 5, 2017Updated 9 years ago
- SVA examples and demonstration☆18Sep 8, 2020Updated 6 years ago
- 1G‑style Ethernet PHY PCS block in Sky130 using OpenLane☆18Feb 15, 2026Updated 7 months ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- Functional Verification the MMU (Memory Management Unit) of a multiprocessor with Data Cache and Instruction Cache☆14Nov 9, 2015Updated 10 years ago
- This repository implements a scaled-down LLaMA 2-like model on an ARM Cortex-M3 soft core, with a custom systolic array RTL module for ef…☆16Jun 25, 2025Updated last year
- uvm auto generator☆23Aug 27, 2018Updated 8 years ago
- Advance UVM testbench with DPI integration, Assertions, Functional Coverage andHierarchical Sequence☆42Jun 24, 2020Updated 6 years ago
- Hardware Implementation of Sigmoid Function using verilog HDL☆16Dec 16, 2019Updated 6 years ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆24Updated this week
- 基于STM32的DCM模式下的BUCK变换器设计☆23Dec 19, 2018Updated 7 years ago
- UVM Generator☆51May 9, 2024Updated 2 years ago
- Replace original DRAM model in GPGPU-sim with Ramulator DRAM model☆22Dec 10, 2018Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- xverif is a local toolkit for chip-verification debug agents. It contains deterministic tools for design and waveform debug, coverage, bi…☆106Sep 25, 2026Updated 2 weeks ago
- Andes Vector Extension support added to riscv-dv☆19May 29, 2020Updated 6 years ago
- UVM Auto Generate ; Verify Project Build; Verilog Instance☆37Apr 15, 2020Updated 6 years ago
- SoC Based on ARM Cortex-M3☆40May 16, 2025Updated last year
- ☆47Aug 23, 2023Updated 3 years ago
- Synchronous FIFO design & verification using systemVerilog Assertions☆20Aug 3, 2021Updated 5 years ago
- Connecting SystemC with SystemVerilog☆43Mar 25, 2012Updated 14 years ago