web版本的SPICE电路仿真平台
☆31Apr 3, 2021Updated 5 years ago
Alternatives and similar repositories for CZ_OpenSpice
Users that are interested in CZ_OpenSpice are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implemention of CapsNet from the paper Dynamic Routing Between Capsules☆10Nov 7, 2017Updated 8 years ago
- Light C++11 graph library☆13Sep 16, 2021Updated 4 years ago
- ☆25Jul 29, 2026Updated last month
- 10_100_1000 Mbps tri-mode ethernet MAC☆11Jul 17, 2014Updated 12 years ago
- Artifacts for the SCVP lecture☆12Nov 17, 2021Updated 4 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- A linear array of PEs with RISC-V ISA targeting extreme high frequency on Xilinx ZYNQ Ultrascale+, specificially for applications such as…☆14Jun 4, 2024Updated 2 years ago
- ☆11Apr 8, 2025Updated last year
- A tiny Python package to parse spice raw data files.☆54Dec 26, 2022Updated 3 years ago
- A Rust-based LEF and DEF file viewer☆15Mar 13, 2026Updated 5 months ago
- ☆17Jan 1, 2021Updated 5 years ago
- This repository contains my work from the VLSI System Design (VSD) Workshop on 7nm FinFET Circuit Design and Characterization using the A…☆16Sep 9, 2025Updated 11 months ago
- MentorGraphics KeyGen & Patch Tool☆19Feb 18, 2022Updated 4 years ago
- Berkeley Analog Generator☆16Apr 3, 2019Updated 7 years ago
- In efforts to solve a dynamic travelling salesman problem☆10Sep 14, 2019Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- A Verilog Filelist parser in Rust☆11Mar 25, 2022Updated 4 years ago
- Wavious Wlink☆12Oct 28, 2021Updated 4 years ago
- RTL modbus rtu slave for FPGA☆14Apr 29, 2022Updated 4 years ago
- Simulation scripts used to create 3D MOSFET example used in: J. E. Sanchez and Q. Chen, "Element Edge Based Discretization for TCAD Devic…☆18Nov 17, 2023Updated 2 years ago
- A tool for making password-protected files☆12Jul 6, 2023Updated 3 years ago
- Powercrust algorithm: from points to a surface mesh and an approximate medial axis☆12Mar 13, 2015Updated 11 years ago
- Advanced Peripheral Bus (APB) UVM testbench project☆10Apr 9, 2017Updated 9 years ago
- A Xtext based SystemRDL editor with syntax highlighting and context sensitive help☆12Feb 9, 2024Updated 2 years ago
- Fast TLB simulator for RISC-V systems☆16May 16, 2019Updated 7 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Basic LLVM passes☆17Oct 7, 2018Updated 7 years ago
- This repository contains an example of the connection between an UVM Testbench and a Python reference model.☆12Nov 6, 2019Updated 6 years ago
- kR^X: Comprehensive Kernel Protection Against Just-In-Time Code Reuse☆13Aug 21, 2017Updated 9 years ago
- A simple cycle accurate template model for ASIC/FPGA hardware design. Including a cycle accurate FIFO design example. More designs are co…☆17Sep 5, 2019Updated 6 years ago
- ☆12Dec 27, 2022Updated 3 years ago
- ☆21Oct 3, 2021Updated 4 years ago
- Schedule for ArtOfSAT☆11Oct 11, 2023Updated 2 years ago
- riscv-linux musl gcc toolchain bootstrap scripts☆18Feb 16, 2021Updated 5 years ago
- Scripts to automate building linux images for my emulator riscv_em☆16Jul 27, 2026Updated last month
- Serverless GPU API endpoints on Runpod - Get Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆16Jan 10, 2025Updated last year
- ☆13Jan 20, 2021Updated 5 years ago
- A Unified Benchmark Environment for Autonomous Flying Robots☆14Jul 12, 2024Updated 2 years ago
- ASCII 🐮s☆12May 23, 2019Updated 7 years ago
- A websocket-based approach to control a desktop application through the web☆20Dec 13, 2018Updated 7 years ago
- UVM components for DSP tasks (MODulation/DEModulation)☆16Mar 2, 2022Updated 4 years ago
- PCIe System Verilog Verification Environment developed for PCIe course☆16Mar 26, 2024Updated 2 years ago