Alternatives and similar repositories for CZ_OpenSpice

Users that are interested in CZ_OpenSpice are comparing it to the libraries listed below

• electronics-and-drives / MLCAD22
  Source code for the Paper: "Deep Reinforcement Learning for Analog Circuit Sizing with an Electrical Design Space and Sparse Rewards"
  ☆15Updated 3 years ago
• ieee-ceda-datc / datc-rdf-Metrics4ML
  ☆32Updated 4 years ago
• jimwang99 / parser-for-chip-design
  A set of Python based parsers for multiple file format used in IC chip design, including Verilog, SPICE, lib (Synopsys Liberty).
  ☆32Updated 10 years ago
• JoseIuri / UVM_Python_UVMC
  This repository contains an example of the connection between an UVM Testbench and a Python reference model using UVM Connect from Mentor…
  ☆17Updated 5 years ago
• ALIGN-analoglayout / AnalogDetailedRouter
  Intel's Analog Detailed Router
  ☆40Updated 6 years ago
• mabrains / Analog_blocks
  Design of Analog Blocks in Skywaters 130nm meeting corners: different flavors of OTA, BandGap, LDO.
  ☆30Updated 3 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆74Updated 6 years ago
• JBlocklove / LLMs-for-EDA-Tutorial
  ☆59Updated 3 weeks ago
• curtisma / VirtuosoToolboxMatlab
  MATLAB toolbox for interfacing with the Cadence Virtuoso IC Design System
  ☆30Updated 8 years ago
• siliconcompiler / lambdalib
  Verilog hardware abstraction library
  ☆45Updated this week
• Ravenslofty / librecell
  ☆26Updated 4 years ago
• ucb-art / laygo
  LAYout with Gridded Objects
  ☆32Updated 5 years ago
• xfguo / tbgen
  Generate testbench for your verilog module.
  ☆38Updated 7 years ago
• acoimbramendes / uart_RTL_to_GDSII
  Project of an integrated UART: RTL, Verification, Physical Implementation (Innovus) and GDSII.
  ☆16Updated 4 years ago
• lnis-uofu / FreePDK45-RRAM-Addon
  A RRAM addon for the NCSU FreePDK 45nm
  ☆25Updated 4 years ago
• ASU-VDA-Lab / ASP-DAC24-Tutorial
  This GitHub repo is for the OpenROAD and CircuitOps Tutorial at ASP-DAC 2024
  ☆54Updated last year
• MichaelMelkor / Vivado_Batch_Mode_Tool
  A tool for those who want to use Vivado's batch mode more easily
  ☆17Updated 6 years ago
• OpenTimer / Parser-Verilog
  A Standalone Structural Verilog Parser
  ☆99Updated 3 years ago
• ckchengucsd / SMT-based-STDCELL-Layout-Generator-for-PROBE2.0
  SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0
  ☆19Updated 5 years ago
• yportne13 / spinalAdderNetMNIST
  SpinalHDL AdderNet MNIST
  ☆11Updated 4 years ago
• Xyce / XDM
  This is the XDM netlist converter, used to convert PSPICE and HSPICE netists into Xyce format.
  ☆22Updated last year
• habibagamal / SoC_Automation
  SoCGen is a tool that automates SoC design by taking in a JSON description of the system and producing the final GDS-II. SoCGen supports …
  ☆39Updated 5 years ago
• PacoReinaCampo / vhdl2verilog
  Hardware Description Language Translator
  ☆17Updated last week
• wmy367 / Radix-2-division
  unsigned Radix-2 SRT division,基2除法
  ☆16Updated 10 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆64Updated 2 years ago
• gmagno / spyci
  A tiny Python package to parse spice raw data files.
  ☆53Updated 3 years ago
• mabrains / caravel_user_project_ldo
  Completed LDO Design for Skywaters 130nm
  ☆19Updated 2 years ago
• gauravtewari / python-to-verilog
  Generate a Verilog Source file and testbench file for a given Moore FSM
  ☆17Updated 13 years ago
• mflowgen / skywater-130nm
  ASIC Design kit for Skywater 130 for use with mflowgen
  ☆14Updated 2 years ago
• paripath / cdf
  Simplify VLSI (timing, power, noise, correlation, reliability) modeling and analysis with Characterization Description Format
  ☆13Updated 5 years ago