Alternatives and similar repositories for smol-gpu

Users that are interested in smol-gpu are comparing it to the libraries listed below

• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆223Updated last year
• cucapra / filament
  Fearless hardware design
  ☆185Updated 4 months ago
• chipsalliance / t1
  ☆306Updated this week
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆55Updated last week
• ecilasun / tinysys
  A tiny system built on a small QMTECH board
  ☆110Updated 9 months ago
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆458Updated this week
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆50Updated last year
• tenstorrent / riscv-ocelot
  Ocelot: The Berkeley Out-of-Order Machine With V-EXT support
  ☆208Updated this week
• fallingcat / HomebrewGPU
  HomebrewGPU is a simple ray tracing GPU built on FPGA, featuring basic ray–primitive intersection, BVH traversal, shadowing, reflection, …
  ☆220Updated 2 years ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆122Updated this week
• MoonbaseOtago / vroom
  VRoom! RISC-V CPU
  ☆514Updated last year
• riscv-software-src / riscv-unified-db
  Monorepo containing a machine-readable database of the RISC-V specification and artifact generation tools
  ☆131Updated this week
• 0BAB1 / HOLY_CORE_COURSE
  Learn how to build our own RV32I(M) core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial wit…
  ☆319Updated last week
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆140Updated 2 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆200Updated this week
• tenstorrent / riscv_arch_tests
  Self checking RISC-V directed tests
  ☆118Updated 7 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆228Updated 2 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆252Updated last year
• pulp-platform / cheshire
  A minimal Linux-capable 64-bit RISC-V SoC built around CVA6
  ☆313Updated last week
• nickmqb / fpga_craft
  A voxel game/Minecraft clone for the iCE40 UP5K FPGA
  ☆208Updated 2 months ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆144Updated this week
• riscv-software-src / riscof
  ☆99Updated 4 months ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆157Updated 3 weeks ago
• spzbrnmrc / Tiny-Vedas
  A highly-configurable RISC-V Core
  ☆28Updated 2 weeks ago
• zeroasiccorp / switchboard
  Communication framework for RTL simulation and emulation.
  ☆307Updated last week
• pulp-platform / mempool
  A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.
  ☆313Updated this week
• bsc-loca / sargantana
  ☆122Updated 5 months ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆81Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆237Updated last year
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆134Updated this week