Grubre / smol-gpuLinks
An rv32i inspired ISA, SIMT GPU implementation in system-verilog.
☆212Updated 10 months ago
Alternatives and similar repositories for smol-gpu
Users that are interested in smol-gpu are comparing it to the libraries listed below
Sorting:
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- ☆304Updated last week
- A configurable RTL to bitstream FPGA toolchain☆55Updated last week
- Fearless hardware design☆184Updated 4 months ago
- A tiny system built on a small QMTECH board☆110Updated 8 months ago
- A new Hardware Design Language that keeps you in the driver's seat☆122Updated last week
- CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…☆454Updated last week
- HomebrewGPU is a simple ray tracing GPU built on FPGA, featuring basic ray–primitive intersection, BVH traversal, shadowing, reflection, …☆216Updated 2 years ago
- VRoom! RISC-V CPU☆514Updated last year
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆205Updated last week
- Like VexRiscv, but, Harder, Better, Faster, Stronger☆190Updated last week
- A highly-configurable RISC-V Core☆27Updated this week
- A scalable 256/1024-RISC-V-core system with low-latency access into shared L1 memory.☆313Updated 2 weeks ago
- ☆120Updated 4 months ago
- 😎 A curated list of awesome RISC-V implementations☆139Updated 2 years ago
- Marginally better than redstone☆102Updated 5 years ago
- RISC-V RV64GC emulator designed for RTL co-simulation☆236Updated last year
- Simple demonstration of using the RISC-V Vector extension☆50Updated last year
- A minimal Linux-capable 64-bit RISC-V SoC built around CVA6☆309Updated this week
- Learn how to build our own RV32I(M) core, verify it and actually use it. From scratch & with more than 200 pages of detailed tutorial wit…☆313Updated this week
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆227Updated 2 years ago
- A voxel game/Minecraft clone for the iCE40 UP5K FPGA☆210Updated last month
- A pipelined RISC-V processor☆63Updated 2 years ago
- Run 64-bit Linux on LiteX + RocketChip☆207Updated 2 months ago
- Communication framework for RTL simulation and emulation.☆305Updated last week
- Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)☆91Updated 2 months ago
- Working Draft of the RISC-V J Extension Specification☆191Updated this week
- A hardware compiler based on LLHD and CIRCT☆264Updated 5 months ago
- An energy-efficient RISC-V floating-point compute cluster.☆118Updated last week
- RISC-V out-of-order core for education and research purposes☆81Updated 2 weeks ago