ecilasun / tinysys

Related projects: ⓘ

• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆162Updated 3 weeks ago
• suarezvictor / CflexHDL
  Design digital circuits in C. Simulate really fast with a regular compiler.
  ☆169Updated last year
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆174Updated 2 weeks ago
• ulixxe / usb_cdc
  Single/Multi-channel Full Speed USB interface for FPGA and ASIC designs
  ☆154Updated 6 months ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆113Updated 3 years ago
• FPGA-Research-Manchester / FABulous
  Fabric generator and CAD tools
  ☆147Updated this week
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆47Updated 9 months ago
• openhwgroup / core-v-cores
  CORE-V Family of RISC-V Cores
  ☆199Updated 7 months ago
• ToNi3141 / RasteriCEr
  Basic OpenGL 1.x implementation for small FPGAs (like iCE40UP5K)
  ☆32Updated 2 years ago
• olofk / corescore
  CoreScore
  ☆135Updated last week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆206Updated 7 months ago
• Domipheus / RPU
  Basic RISC-V CPU implementation in VHDL.
  ☆158Updated 4 years ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆70Updated 2 weeks ago
• pieter3d / simview
  ☆76Updated 6 months ago
• davidthings / tinyfpga_bx_usbserial
  USB Serial on the TinyFPGA BX
  ☆131Updated 3 years ago
• projf / display_controller
  FPGA display controller with support for VGA, DVI, and HDMI.
  ☆205Updated 4 years ago
• laforest / FPGADesignElements
  A self-contained online book containing a library of FPGA design modules and related coding/design guides.
  ☆387Updated this week
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆69Updated last year
• icebreaker-fpga / icebreaker-verilog-examples
  This repository contains small example designs that can be used with the open source icestorm flow.
  ☆136Updated 2 years ago
• chipsalliance / synlig
  SystemVerilog support for Yosys
  ☆156Updated this week
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆89Updated last month
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆79Updated last year
• openhwgroup / cvw
  CORE-V Wally is a configurable RISC-V Processor associated with RISC-V System-on-Chip Design textbook. Contains a 5-stage pipeline, suppo…
  ☆237Updated this week
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆35Updated last year
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆104Updated this week
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆111Updated 2 years ago
• olofk / vidbo
  Virtual Development Board
  ☆57Updated 2 years ago
• lakshmi-sathi / avsdpll_1v8
  8x PLL Clock Multiplier IP with an input frequency range of 5Mhz to 12.5Mhz and output frequency range of 40Mhz to 100Mhz, giving a 8x mu…
  ☆107Updated 3 years ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆105Updated last month
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆107Updated 11 months ago