Alternatives and similar repositories for moss

Users that are interested in moss are comparing it to the libraries listed below

• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆221Updated last year
• olofk / corescore
  CoreScore
  ☆162Updated last week
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆139Updated 4 months ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆113Updated 3 years ago
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆87Updated last week
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 3 months ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆57Updated last year
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• pc2 / sus-compiler
  A new Hardware Design Language that keeps you in the driver's seat
  ☆114Updated this week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆105Updated last week
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆144Updated last year
• oxidecomputer / cobalt
  A collection of common Bluespec interfaces/modules.
  ☆102Updated last year
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆92Updated 10 months ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆60Updated 3 weeks ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆87Updated last month
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆58Updated last week
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆111Updated last month
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆41Updated last week
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆179Updated last week
• mnemocron / my-discrete-fpga
  My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.
  ☆43Updated last year
• mole99 / greyhound-ihp
  Greyhound on IHP SG13G2 0.13 μm BiCMOS process
  ☆52Updated 3 weeks ago
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆71Updated this week
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆52Updated 3 months ago
• sylefeb / Iron
  Iron: selectively turn RISC-V binaries into hardware
  ☆23Updated 2 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆151Updated 2 months ago
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆118Updated 4 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆107Updated last year