mosscomp / moss

Related projects ⓘ

Alternatives and complementary repositories for moss

• olofk / corescore
  CoreScore
  ☆139Updated 2 months ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆74Updated last month
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆130Updated last year
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 3 years ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 2 years ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆112Updated 2 weeks ago
• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆204Updated 7 months ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆84Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆131Updated 3 weeks ago
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆73Updated 2 months ago
• sylefeb / Silixel
  Exploring gate level simulation
  ☆56Updated 2 years ago
• rsnikhil / Learn_Bluespec_and_RISCV_Design
  Textbook and full source codes to learn basics of RISC-V pipelined CPU design using the Bluespec Hardware Design Language(s)
  ☆54Updated 2 months ago
• SpinalHDL / SaxonSoc
  SoC based on VexRiscv and ICE40 UP5K
  ☆150Updated 7 months ago
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆142Updated 10 months ago
• bl0x / learn-fpga-amaranth
  Code for Bruno Levy's learn-fpga tutorial written in Amaranth HDL
  ☆89Updated 4 months ago
• smunaut / doom_riscv
  Doom classic port to lightweight RISC‑V
  ☆83Updated 2 years ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆131Updated last month
• stnolting / fpga_puf
  Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.
  ☆126Updated 2 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆48Updated 11 months ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆218Updated last year
• antonblanchard / vlsiffra
  Create fast and efficient standard cell based adders, multipliers and multiply-adders.
  ☆110Updated last year
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆57Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆165Updated this week
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆107Updated last month
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆217Updated 2 weeks ago
• cucapra / filament
  Fearless hardware design
  ☆162Updated this week
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆213Updated last month
• efabless / caravel_mpw-one
  Caravel is a standard SoC hardness with on chip resources to control and read/write operations from a user-dedicated space.
  ☆135Updated 2 years ago
• riscv / configuration-structure
  RISC-V Configuration Structure
  ☆37Updated 3 weeks ago
• chipsalliance / fpga-tool-perf
  FPGA tool performance profiling
  ☆102Updated 9 months ago