mosscomp / mossLinks
A computer for human beings.
☆47Updated last year
Alternatives and similar repositories for moss
Users that are interested in moss are comparing it to the libraries listed below
Sorting:
- Minimax: a Compressed-First, Microcoded RISC-V CPU☆222Updated last year
- CoreScore☆169Updated 3 weeks ago
- A configurable and approachable tool for FPGA debugging and rapid prototyping.☆144Updated 7 months ago
- RISC-V out-of-order core for education and research purposes☆81Updated last week
- System on Chip toolkit for Amaranth HDL☆97Updated last year
- A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.☆19Updated 3 years ago
- A configurable RTL to bitstream FPGA toolchain☆54Updated last week
- 😎 A curated list of awesome RISC-V implementations☆139Updated 2 years ago
- Exploring gate level simulation☆58Updated 7 months ago
- A collection of common Bluespec interfaces/modules.☆102Updated last year
- End-to-end synthesis and P&R toolchain☆92Updated 2 months ago
- PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers☆62Updated 7 months ago
- cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.☆115Updated 3 months ago
- Naive Educational RISC V processor☆92Updated last month
- Example LED blinking project for your FPGA dev board of choice☆187Updated last month
- User-friendly explanation of Yosys options☆113Updated 4 years ago
- A pipelined RISC-V processor☆62Updated 2 years ago
- A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.☆108Updated 3 weeks ago
- Documenting Lattice's 28nm FPGA parts☆145Updated last year
- Unofficial Yosys WebAssembly packages☆74Updated this week
- Dual-issue RV64IM processor for fun & learning☆64Updated 2 years ago
- Another size-optimized RISC-V CPU for your consideration.☆58Updated last month
- ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!☆226Updated 2 years ago
- RISC-V Processor written in Amaranth HDL☆39Updated 3 years ago
- RISC-V Configuration Structure☆41Updated last year
- 4 stage, in-order, secure RISC-V core based on the CV32E40P☆151Updated last year
- Universal Memory Interface (UMI)☆153Updated last week
- My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.☆46Updated last year
- ☆71Updated last year
- Linux capable RISC-V SoC designed to be readable and useful.☆154Updated 6 months ago