Alternatives and similar repositories for moss

Users that are interested in moss are comparing it to the libraries listed below

• gsmecher / minimax
  Minimax: a Compressed-First, Microcoded RISC-V CPU
  ☆221Updated last year
• olofk / corescore
  CoreScore
  ☆164Updated 2 months ago
• fischermoseley / manta
  A configurable and approachable tool for FPGA debugging and rapid prototyping.
  ☆140Updated 6 months ago
• lachlansneff / ligeia
  A replacement for gtkwave, written in Rust with high-performance and larger-than-memory traces in mind.
  ☆19Updated 3 years ago
• Ravenslofty / yosys-cookbook
  User-friendly explanation of Yosys options
  ☆112Updated 4 years ago
• drom / awesome-riscv
  😎 A curated list of awesome RISC-V implementations
  ☆138Updated 2 years ago
• YosysHQ / nerv
  Naive Educational RISC V processor
  ☆89Updated last week
• siliconcompiler / logik
  A configurable RTL to bitstream FPGA toolchain
  ☆46Updated this week
• prjunnamed / prjunnamed
  End-to-end synthesis and P&R toolchain
  ☆89Updated last month
• gatecat / prjoxide
  Documenting Lattice's 28nm FPGA parts
  ☆144Updated last year
• kuznia-rdzeni / coreblocks
  RISC-V out-of-order core for education and research purposes
  ☆65Updated 3 weeks ago
• zephray / RISu064
  Dual-issue RV64IM processor for fun & learning
  ☆64Updated 2 years ago
• amaranth-lang / amaranth-soc
  System on Chip toolkit for Amaranth HDL
  ☆95Updated last year
• fusesoc / blinky
  Example LED blinking project for your FPGA dev board of choice
  ☆185Updated last week
• regymm / pcie_7x
  PCIe Endpoint on Xilinx 7-Series FPGAs with the PCIE_2_1 hard block and GTP transceivers
  ☆61Updated 5 months ago
• minerva-cpu / minerva
  A 32-bit RISC-V soft processor
  ☆315Updated 3 months ago
• betrusted-io / betrusted-soc
  Betrusted main SoC design
  ☆147Updated 3 months ago
• oxidecomputer / cobalt
  A collection of common Bluespec interfaces/modules.
  ☆102Updated last year
• sylefeb / Silixel
  Exploring gate level simulation
  ☆58Updated 6 months ago
• cr1901 / sentinel
  Another size-optimized RISC-V CPU for your consideration.
  ☆57Updated 3 weeks ago
• regymm / quasiSoC
  Linux capable RISC-V SoC designed to be readable and useful.
  ☆152Updated 5 months ago
• microsoft / cheriot-ibex
  cheriot-ibex is a RTL implementation of CHERIoT ISA based on LowRISC's Ibex core.
  ☆113Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 11 months ago
• brouhaha / glacial
  Glacial - microcoded RISC-V core designed for low FPGA resource utilization
  ☆86Updated 5 years ago
• BrunoLevy / TordBoyau
  A pipelined RISC-V processor
  ☆62Updated last year
• YoWASP / yosys
  Unofficial Yosys WebAssembly packages
  ☆73Updated this week
• meiniKi / FazyRV
  A minimal-area RISC-V core with a scalable data path to 1, 2, 4, or 8 bits and manifold variants.
  ☆107Updated last month
• amaranth-lang / amaranth-boards
  Board definitions for Amaranth HDL
  ☆120Updated last month
• gatecat / nextpnr-xilinx
  Experimental flows using nextpnr for Xilinx devices
  ☆246Updated last year
• litex-hub / fpga_101
  FPGA 101 lessons/labs
  ☆393Updated last year