kgpai94 / ECC-Encryption-SystemLinks
This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
☆31Updated 7 years ago
Alternatives and similar repositories for ECC-Encryption-System
Users that are interested in ECC-Encryption-System are comparing it to the libraries listed below
Sorting:
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Updated 6 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆41Updated 5 years ago
- Generic FIFO implementation with optional FWFT☆60Updated 5 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆84Updated 7 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Updated 8 years ago
- ☆69Updated 4 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆50Updated 10 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆66Updated 5 years ago
- DDR4 Simulation Project in System Verilog☆42Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆31Updated 7 years ago
- FPGA implementation of Chinese SM4 encryption algorithm.☆56Updated 7 years ago
- DMA Hardware Description with Verilog☆18Updated 5 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆71Updated 6 months ago
- ☆79Updated 3 years ago
- System Verilog and Emulation. Written all the five channels.☆35Updated 8 years ago
- SDRAM controller with AXI4 interface☆98Updated 6 years ago
- Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps☆46Updated 2 years ago
- 4096bit RSA project, with verilog code, python test code, etc☆47Updated 6 years ago
- General Purpose AXI Direct Memory Access☆61Updated last year
- Xilinx PCIe to MIG DDR4 example designs and custom part data files☆39Updated last year
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Updated 4 years ago
- Parameterised Asynchronous AHB3-Lite to APB4 Bridge.☆47Updated last year
- I2C controller core☆47Updated 2 years ago
- Implementation of the PCIe physical layer☆57Updated 4 months ago
- Basic floating-point components for RISC-V processors☆67Updated 5 years ago
- 256-bit vector processor based on the RISC-V vector (V) extension☆31Updated 4 years ago
- AMBA bus generator including AXI, AHB, and APB☆108Updated 4 years ago
- An FPGA-based GZIP (Deflate algorithm) compressor, which inputs raw data and outputs standard GZIP format (as known as .gz file format). …☆144Updated 2 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- RTL Verilog library for various DSP modules☆92Updated 3 years ago