This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
☆31Sep 24, 2018Updated 7 years ago
Alternatives and similar repositories for ECC-Encryption-System
Users that are interested in ECC-Encryption-System are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆24Feb 20, 2017Updated 9 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆21Oct 31, 2017Updated 8 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 11 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 6 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 5 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆27Aug 1, 2018Updated 7 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆58Apr 3, 2025Updated last year
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆47Nov 24, 2025Updated 5 months ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆140Jul 31, 2022Updated 3 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆24Oct 15, 2025Updated 7 months ago
- XFS readonly driver for Windows☆15Jun 30, 2012Updated 13 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- ☆30Mar 1, 2025Updated last year
- RTL blocks compatible with the Rocket Chip Generator☆17Mar 30, 2025Updated last year
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- Dilithium is a digital signature scheme that is strongly secure under chosen message attacks based on the hardness of lattice problems ov…☆17Jul 28, 2023Updated 2 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…☆31Nov 9, 2015Updated 10 years ago
- 编程百科☆33Mar 15, 2014Updated 12 years ago
- Barerbones OSX based Verilog simulation toolchain.☆20Nov 1, 2020Updated 5 years ago
- Cobo Vault developer Documents☆13Mar 17, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- ☆19Mar 6, 2020Updated 6 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆11Aug 15, 2020Updated 5 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- 东南大学第一届物联网设计竞赛：基于乐鑫科技M5 GO和歪朵拉 AIRV r2的家用水表检测物联网检测设备☆16May 10, 2020Updated 6 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- This paper presents design of UART module for serial communication used for short-distance, low speed and exchange of data between comput…☆15Mar 30, 2022Updated 4 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆12Sep 2, 2016Updated 9 years ago
- HW Design Collateral for Caliptra RoT IP☆138May 15, 2026Updated last week
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆22Dec 11, 2023Updated 2 years ago
- 异步FIFO的内部实现☆25Aug 26, 2018Updated 7 years ago
- Verilog HDL implementation of an ECHO machine and an FIR filter that filters out a specific noise. More details provided in individual fi…☆10Aug 25, 2019Updated 6 years ago
- BlackParrot on Zynq☆55Apr 21, 2026Updated last month