Alternatives and similar repositories for ECC-Encryption-System

Users that are interested in ECC-Encryption-System are comparing it to the libraries listed below

• crypt-xie / XCryptCore
  Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)
  ☆40Updated 5 years ago
• mematrix / AES-FPGA
  AES加密解密算法的Verilog实现
  ☆66Updated 9 years ago
• shiva-t / Elliptical-Curve-Cryptography-FPGA
  Implementation of ECC on FPGA-Zynq7000 SoC
  ☆19Updated 6 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆60Updated 5 years ago
• yvnr4you / AMBA_AXI3
  System Verilog and Emulation. Written all the five channels.
  ☆34Updated 8 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆58Updated last year
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆90Updated 3 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• raymondrc / FPGA_SM4
  FPGA implementation of Chinese SM4 encryption algorithm.
  ☆56Updated 7 years ago
• antmicro / nvme-verilog-pcie
  ☆78Updated 3 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 5 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆106Updated 4 years ago
• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆65Updated 4 months ago
• bhunt2 / DDR4Sim
  DDR4 Simulation Project in System Verilog
  ☆41Updated 11 years ago
• oprecomp / DDR4_controller
  ☆64Updated 4 years ago
• ultraembedded / core_sdram_axi4
  SDRAM controller with AXI4 interface
  ☆98Updated 6 years ago
• RoaLogic / ahb3lite_apb_bridge
  Parameterised Asynchronous AHB3-Lite to APB4 Bridge.
  ☆45Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆65Updated 5 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆111Updated 3 years ago
• russdill / bch_verilog
  Verilog based BCH encoder/decoder
  ☆124Updated 2 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆62Updated 4 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆96Updated 5 years ago
• pansygrass / ecc
  Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…
  ☆48Updated 10 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• d953i / Custom_Part_Data_Files
  Xilinx PCIe to MIG DDR4 example designs and custom part data files
  ☆39Updated last year
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆17Updated 5 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆66Updated 5 years ago
• zhajio1988 / ExtremeDV_UVM
  UVM resource from github, run simulation use YASAsim flow
  ☆30Updated 5 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆75Updated 11 years ago