This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
☆31Sep 24, 2018Updated 7 years ago
Alternatives and similar repositories for ECC-Encryption-System
Users that are interested in ECC-Encryption-System are comparing it to the libraries listed below
Sorting:
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆23Feb 20, 2017Updated 9 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆10Jan 14, 2024Updated 2 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 10 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆21Apr 15, 2021Updated 4 years ago
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆46Nov 24, 2025Updated 3 months ago
- A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…☆12Jan 5, 2023Updated 3 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 7 years ago
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆134Jul 31, 2022Updated 3 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆24Oct 15, 2025Updated 5 months ago
- XFS readonly driver for Windows☆15Jun 30, 2012Updated 13 years ago
- Digital Image Processing Algorithms in MATLAB☆12Jun 18, 2018Updated 7 years ago
- The verilog code together with cocotb testbench of BFU unit of a DIF FFT processor☆15Apr 11, 2023Updated 2 years ago
- UVM examples☆14May 1, 2015Updated 10 years ago
- just to compare perf between mojo, nim, java, nodejs, rust and python3 of a same algo☆16Updated this week
- Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores☆13Feb 23, 2025Updated last year
- ☆29Mar 1, 2025Updated last year
- A RISC-V processor in system verilog☆12Jul 9, 2020Updated 5 years ago
- Dilithium is a digital signature scheme that is strongly secure under chosen message attacks based on the hardness of lattice problems ov…☆15Jul 28, 2023Updated 2 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…☆30Nov 9, 2015Updated 10 years ago
- FIR band-pass filter using Verilog HDL.☆13Sep 6, 2020Updated 5 years ago
- An Image Encryption Scheme Based on Chaotic Logarithmic Map and Key Generation using Deep CNN☆19Dec 29, 2020Updated 5 years ago
- 编程百科☆33Mar 15, 2014Updated 12 years ago
- Barerbones OSX based Verilog simulation toolchain.☆20Nov 1, 2020Updated 5 years ago
- Cobo Vault developer Documents☆13Mar 17, 2021Updated 5 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emula…☆17Mar 22, 2017Updated 9 years ago
- ☆19Mar 6, 2020Updated 6 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- ECE563 Final Project - FPGA based camera tracking☆18Dec 17, 2013Updated 12 years ago
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆17Sep 23, 2020Updated 5 years ago
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- BlackParrot on Zynq☆53Mar 16, 2026Updated last week
- A deep learning based bioinformatics project on epigenetics in Type 2 Diabetes.☆17Mar 25, 2023Updated 2 years ago
- Traces for SVA - SystemVerilog Assertions; Will use Go2UVM package to write traces and use uvm_report_mock to predict errors☆11Sep 2, 2016Updated 9 years ago
- Verilog HDL implementation of the GOST 28147-89 — a Soviet and Russian government standard symmetric key block cipher☆17Feb 27, 2024Updated 2 years ago