This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Elliptic Curve Cryptography. This project was implemented using a spartan 3 FPGA kit.
☆32Sep 24, 2018Updated 7 years ago
Alternatives and similar repositories for ECC-Encryption-System
Users that are interested in ECC-Encryption-System are comparing it to the libraries listed below
Sorting:
- Implementation of ECC on FPGA-Zynq7000 SoC☆19Jul 12, 2019Updated 6 years ago
- Research Interan@BARC FPGA based High-Throughput Generic ECC Implementation in Binary Extension Field☆24Feb 20, 2017Updated 9 years ago
- Verilog HDL implementation of Elliptic Curve Cryptography (ECC) over GF(2^163)☆22Oct 31, 2017Updated 8 years ago
- Error correction and detection example Verilog (hamming and Reed-Solomon) to accompany presentation material☆11Jan 14, 2024Updated 2 years ago
- Verilog for a SECDED Hsaio ECC and a DEC ECC. Power, delay, and area are compared for Berkeley MASIC EEW241B - Advanced Digital Integrate…☆55Apr 29, 2015Updated 10 years ago
- Design a median filter for a Generic RGB image.☆14Mar 6, 2019Updated 6 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆36Feb 21, 2024Updated 2 years ago
- XFS readonly driver for Windows☆15Jun 30, 2012Updated 13 years ago
- Framework to perform DUT vs ISS (Whisper) lockstep architectural checks☆24Oct 15, 2025Updated 4 months ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆22Apr 15, 2021Updated 4 years ago
- This is a project meant to be run on an FPGA that was Implemented in the Verilog HDL using Xilinx ISE design suite.☆26May 12, 2020Updated 5 years ago
- Verilog implementation of the SHA-1 cryptgraphic hash function☆57Apr 3, 2025Updated 11 months ago
- ☆29Mar 1, 2025Updated last year
- ☆37Feb 20, 2026Updated last week
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆131Jul 31, 2022Updated 3 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆29Nov 9, 2015Updated 10 years ago
- Verilog Code for a JPEG Decoder☆34Mar 7, 2018Updated 7 years ago
- Implementation of RSA algorithm on FPGA using Verilog☆28Aug 1, 2018Updated 7 years ago
- Kernel mode to user mode dll injection.☆14Nov 10, 2024Updated last year
- Verilog implementation of SHA1/SHA224/SHA256/SHA384/SHA512. 使用Verilog实现的SHA1/SHA224/SHA256/SHA384/SHA512计算器。☆81Sep 14, 2023Updated 2 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆86Feb 28, 2018Updated 8 years ago
- 二维码扫描、生成☆11Sep 6, 2013Updated 12 years ago
- Este projeto é fruto de um estudo pessoal sobre o algoritmo Secp256k1. O objetivo dele é conseguir obter, usando apenas os valores da cha…☆12Dec 7, 2022Updated 3 years ago
- to study xilinx fpga using Zybo Z7-20 board☆14Mar 13, 2024Updated last year
- A driver created to bypass the anti-cheat and r/w memory through it☆15Aug 3, 2024Updated last year
- A VHDL IP for ECC (Elliptic Curve Cryptography) hardware acceleration☆46Nov 24, 2025Updated 3 months ago
- FIR band-pass filter using Verilog HDL.☆12Sep 6, 2020Updated 5 years ago
- A simple implementation of a UART modem in Verilog.☆175Nov 10, 2021Updated 4 years ago
- A design of 15-order FIR filter using Verilog, with modulation and demodulation system using MATLAB☆10Aug 15, 2020Updated 5 years ago
- The ASN.1 Compiler☆10Nov 14, 2023Updated 2 years ago
- Utility scripts to configure processors, perform synthesis, load onto FPGAs, and other tasks related to ProcessorCI.☆17Dec 7, 2025Updated 2 months ago
- Mirror only see https://gitlab.rtems.org/rtems/docs/rtems-docs/☆10Feb 21, 2026Updated last week
- Windows PE file debugger☆11Aug 30, 2017Updated 8 years ago
- 用ffmpeg+QT写的播放rtsp等流媒体的视频播放器☆12Dec 6, 2016Updated 9 years ago
- MD5 core in verilog☆13May 1, 2012Updated 13 years ago
- Windows driver for DroidPad☆12Apr 12, 2014Updated 11 years ago
- ☆10Updated this week
- Complete ASIC Design of UART Interface with Baud Rate Selection :- RTL to GDS2☆12Sep 3, 2019Updated 6 years ago
- 每天一个技术点☆10Sep 10, 2023Updated 2 years ago