ChairImpSec / PROLEAD
PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software
☆36Updated 2 weeks ago
Alternatives and similar repositories for PROLEAD:
Users that are interested in PROLEAD are comparing it to the libraries listed below
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆21Updated 3 months ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆34Updated 3 years ago
- Side-Channel Analysis Library☆77Updated last week
- Side-channel analysis setup for OpenTitan☆29Updated this week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆45Updated 2 weeks ago
- SILVER - Statistical Independence and Leakage Verification☆13Updated 2 years ago
- HW Design Collateral for Caliptra RoT IP☆79Updated this week
- Design files and associated documentation for Sonata PCB, part of the Sunburst Project☆14Updated this week
- Iodine: Verifying Constant-Time Execution of Hardware☆12Updated 3 years ago
- Development Package for the Hardware API for Lightweight Cryptography☆15Updated last year
- Optimized assembly implementations of crypto for the RV32I (RISC-V) architecture☆31Updated 4 years ago
- Data oblivious ISA prototyped on the RISC-V BOOM processor.☆20Updated 2 years ago
- SMT Attack☆20Updated 3 years ago
- ☆21Updated 4 years ago
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆14Updated 4 years ago
- Testing processors with Random Instruction Generation☆30Updated last week
- ☆18Updated 6 months ago
- Code repository for Coppelia tool☆22Updated 4 years ago
- Open Source AES☆31Updated 9 months ago
- VexRiscv reference platforms for the pqriscv project☆15Updated 10 months ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆127Updated 2 years ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆61Updated 5 years ago
- A port of the RIPE suite to RISC-V.☆28Updated 6 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆28Updated 10 months ago
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆24Updated last year
- Naive Educational RISC-V -- A simple single-stage RV32I processor☆25Updated 4 years ago
- ☆81Updated last year
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆33Updated last year
- A fault-injection framework using Chisel and FIRRTL☆34Updated last year
- XCrypto: a cryptographic ISE for RISC-V☆92Updated 2 years ago