ChairImpSec / PROLEADLinks
PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software
☆40Updated last week
Alternatives and similar repositories for PROLEAD
Users that are interested in PROLEAD are comparing it to the libraries listed below
Sorting:
- SILVER - Statistical Independence and Leakage Verification☆14Updated 2 months ago
- HW Design Collateral for Caliptra RoT IP☆103Updated this week
- The SpinalHDL design of the Proteus core, an extensible RISC-V core.☆55Updated 3 weeks ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Side-Channel Analysis Library☆96Updated 3 weeks ago
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4☆36Updated 4 years ago
- Side-channel analysis setup for OpenTitan☆35Updated 2 weeks ago
- ☆64Updated 2 months ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 10 months ago
- Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)☆64Updated 5 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆69Updated 4 months ago
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆26Updated last year
- Implementation of Tagged Memory security policies into Rocket Core☆10Updated 8 years ago
- ☆40Updated last month
- VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against …☆19Updated 5 years ago
- Testing processors with Random Instruction Generation☆44Updated last month
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆33Updated this week
- Development Package for the Hardware API for Lightweight Cryptography☆16Updated 4 months ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆134Updated 2 years ago
- Hardware Design of Ascon☆23Updated 2 weeks ago
- rfuzz: coverage-directed fuzzing for RTL research platform☆108Updated 3 years ago
- Amazon F1-inspired Xilinx VCU118 hardware design framework☆12Updated 4 years ago
- Bitfiltrator: A general approach for reverse-engineering Xilinx bitstream formats☆44Updated 2 years ago
- All the tools you need to reproduce the CellIFT paper experiments☆21Updated 5 months ago
- BUSted!!! Microarchitectural Side-Channel Attacks on the MCU Bus Interconnect☆11Updated last year
- This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 is Hex Five's official reference HW p…☆31Updated last year
- This specification will define the RISC-V privilege ISA extensions required to support Supervisor Domain isolation for multi-tenant secur…☆58Updated this week
- Test suite containing a reproduction of all major transient-execution attacks in RISC-V and CHERI-RISC-V assembly☆15Updated 4 years ago