Alternatives and similar repositories for VerMFi

Users that are interested in VerMFi are comparing it to the libraries listed below

• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆37Updated 2 months ago
• isec-tugraz / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆24Updated last year
• sca-research / ELMO
  ☆54Updated last year
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆16Updated last year
• simple-crypto / SCALib
  Side-Channel Analysis Library
  ☆105Updated 5 months ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆22Updated 4 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆27Updated 4 years ago
• newaetech / CW305-Arm-DesignStart
  Instruction and files for porting Arm DesignStart to CW305.
  ☆16Updated 2 years ago
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆14Updated 7 months ago
• chipsalliance / adams-bridge
  Post-Quantum Cryptography IP Core (Crystals-Dilithium)
  ☆43Updated this week
• ChairImpSec / PROLEAD
  PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software　　　　　　　　　　　　　FIESTA - Fault Injection Evaluation with Statistic…
  ☆41Updated last week
• ikizhvatov / pysca
  Toolbox for advanced differential power analysis of symmetric key cryptographic algorithm implementations
  ☆49Updated 7 years ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆77Updated 2 months ago
• nils-wisiol / pypuf
  Cryptanalysis of Physically Unclonable Functions
  ☆91Updated last year
• antmicro / rowhammer-tester
  ☆73Updated last week
• riscv-boom / boom-attacks
  Proof of concepts for speculative attacks using the BOOM core (https://github.com/riscv-boom/riscv-boom)
  ☆68Updated 6 years ago
• rprimas / ascon-verilog
  Hardware Design of Ascon
  ☆35Updated this week
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆16Updated 5 years ago
• emsec / ImpeccableCircuits
  Hardware designs for fault detection
  ☆19Updated 5 years ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆29Updated 7 years ago
• ZSusskind / vcd2csv
  Extracts specified data from a VCD file into CSV form
  ☆10Updated 6 years ago
• Secure-Embedded-Systems / Masked-AES-Implementation
  ☆23Updated 5 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆61Updated 2 weeks ago
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆33Updated 8 years ago
• PrincetonUniversity / AutoSVA
  AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…
  ☆98Updated last year
• socsecresearch / SoC_Vulnerability_Benchmarks
  ☆11Updated 9 months ago
• AISyLab / side-channel-analysis-toolbox
  This is a project in which side-channel attacks are researched and developed.
  ☆51Updated 5 years ago
• openhwgroup / cva6-platform
  CVA6-platform is a multicore CVA6 with CV-MESH software and regression platform
  ☆12Updated 2 years ago
• AISyLab / AISY_Framework
  Deep Learning-based Framework for Side-Channel Analysis
  ☆39Updated 3 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆55Updated 5 years ago