vmarribas / VerMFiLinks
VerMFi: Verification tool for Masked implementations and Fault injection. Set of tools to evaluate resistance of secure hardware against Side-Channel attacks and Fault Attacks
☆18Updated 5 years ago
Alternatives and similar repositories for VerMFi
Users that are interested in VerMFi are comparing it to the libraries listed below
Sorting:
- Side-channel analysis setup for OpenTitan☆32Updated last month
- ☆48Updated last year
- Side-Channel Analysis Library☆90Updated 3 weeks ago
- CocoAlma is an execution-aware tool for formal verification of masked implementations☆22Updated 8 months ago
- ☆23Updated 5 years ago
- Toolbox for advanced differential power analysis of symmetric key cryptographic algorithm implementations☆49Updated 6 years ago
- SILVER - Statistical Independence and Leakage Verification☆14Updated 2 years ago
- Deep Learning-based Framework for Side-Channel Analysis☆34Updated 3 years ago
- Post-Quantum Cryptography IP Core (Crystals-Dilithium)☆28Updated this week
- Tutorials and examples on how to use Jlsca, the high-performance side channel analysis toolkit written in Julia☆50Updated 5 years ago
- A curated list of awesome side-channel attack resources☆80Updated last year
- PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software☆40Updated this week
- A port of the RIPE suite to RISC-V.☆29Updated 6 years ago
- Verilog Hardware Design of Ascon☆22Updated last week
- NIST LWC Hardware Reference Implementation of Ascon v1.2☆26Updated last year
- ☆15Updated 5 months ago
- VexRiscv reference platforms for the pqriscv project☆16Updated last year
- Masked Hardware AES with HPC☆13Updated 7 months ago
- An open-source deterministic fault attack simulator prototype☆58Updated 4 years ago
- Make your first side-channel attack on public datasets with eShard. This is a mirror of scared Gitlab repository. All contributions and m…☆91Updated 2 weeks ago
- FPGA implementation of a physical unclonable function for authentication☆32Updated 8 years ago
- Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)☆67Updated 2 months ago
- ☆83Updated 2 years ago
- This is a project in which side-channel attacks are researched and developed.☆46Updated 5 years ago
- Simple deep learning side channel attack. Experimental data set based on chipwhisperer.☆29Updated 3 years ago
- Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)☆16Updated 4 years ago
- ☆14Updated 7 years ago
- Cryptanalysis of Physically Unclonable Functions☆87Updated 11 months ago
- NIST LWC Hardware Design of Ascon with Protection against Power Side-Channel Attacks☆17Updated 2 years ago
- Code repository for Coppelia tool☆23Updated 4 years ago