vmarribas / VerMFi

Related projects ⓘ

Alternatives and complementary repositories for VerMFi

• Secure-Embedded-Systems / Masked-AES-Implementation
  ☆21Updated 4 years ago
• IAIK / coco-alma
  CocoAlma is an execution-aware tool for formal verification of masked implementations
  ☆21Updated last month
• lowRISC / ot-sca
  Side-channel analysis setup for OpenTitan
  ☆28Updated last month
• Chair-for-Security-Engineering / AES_masked_BRAM
  Designs of first-order SCA-secure hardware implementations of AES encryption/decryptoin dedicated to Xilinx FPGAs (using BRAM)
  ☆14Updated 3 years ago
• rprimas / ascon-verilog
  Verilog Hardware Design of Ascon v1.2
  ☆19Updated this week
• ChairImpSec / PROLEAD
  PROLEAD - A Probing-Based Leakage Detection Tool for Hardware and Software
  ☆32Updated this week
• simple-crypto / SCALib
  Side-Channel Analysis Library
  ☆74Updated 2 months ago
• scluconn / LPN-based_PUF
  FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.
  ☆15Updated 7 years ago
• scarv / scarv
  SCARV: a side-channel hardened RISC-V platform
  ☆18Updated 3 years ago
• GMUCERG / Dilithium
  High-speed full CRYSTALS-DILITHIUM implementation on FPGA: Keygen, Sign, Verify.
  ☆41Updated last year
• Chair-for-Security-Engineering / SILVER
  SILVER - Statistical Independence and Leakage Verification
  ☆12Updated last year
• eriksargent / PUF-lab
  FPGA implementation of a physical unclonable function for authentication
  ☆31Updated 7 years ago
• hadipourh / CryptoHDL
  A list of VHDL codes implementing cryptographic algorithms
  ☆25Updated 2 years ago
• scluconn / DA_PUF_Library
  Defense/Attack PUF Library (DA PUF Library)
  ☆45Updated 4 years ago
• mupq / pqriscv-vexriscv
  VexRiscv reference platforms for the pqriscv project
  ☆15Updated 8 months ago
• draperlaboratory / hope-RIPE
  A port of the RIPE suite to RISC-V.
  ☆28Updated 6 years ago
• chipsalliance / caliptra-rtl
  HW Design Collateral for Caliptra RoT IP
  ☆76Updated this week
• mjosaarinen / lwaes_isa
  [HISTORICAL] A Lightweight (RISC-V) ISA Extension for AES and SM4
  ☆34Updated 3 years ago
• sca-research / ELMO
  ☆45Updated 5 months ago
• gatelabdavis / SMTAttack
  SMT Attack
  ☆18Updated 3 years ago
• morenes / AutoCC
  Methodology that leverages FPV to automatically discover covert channels in hardware that is time-shared between processes. AutoCC operat…
  ☆13Updated 2 weeks ago
• antmicro / rowhammer-tester
  ☆55Updated this week
• secworks / modexp
  Modular Exponentiation core written i Verilog. Supports key lengths between 32 and 8192 bits.
  ☆17Updated 4 years ago
• proteus-core / proteus
  The SpinalHDL design of the Proteus core, an extensible RISC-V core.
  ☆42Updated last month
• nils-wisiol / pypuf
  Cryptanalysis of Physically Unclonable Functions
  ☆78Updated 4 months ago
• AISyLab / AISY_Framework
  Deep Learning-based Framework for Side-Channel Analysis
  ☆29Updated 2 years ago
• Keysight / FiSim
  An open-source deterministic fault attack simulator prototype
  ☆49Updated 3 years ago
• mit-ll / CEP
  The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freel…
  ☆60Updated last year
• newaetech / sonata-pcb
  Design files and associated documentation for Sonata PCB, part of the Sunburst Project
  ☆13Updated 4 months ago
• cispa / Security-RISC
  Proof-of-concept implementation for the paper "A Security RISC: Microarchitectural Attacks on Hardware RISC-V CPUs" (IEEE S&P 2023)
  ☆54Updated 3 months ago