Alternatives and similar repositories for hVHDL_example_project

Users that are interested in hVHDL_example_project are comparing it to the libraries listed below

• gsmecher / pyxsi
  Python/C/RTL cosimulation with Xilinx's xsim simulator
  ☆70Updated 9 months ago
• hdl-registers / hdl-registers
  An open-source HDL register code generator fast enough to run in real time.
  ☆71Updated last week
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆33Updated 4 months ago
• tmeissner / libvhdl
  Library of reusable VHDL components
  ☆28Updated last year
• tarik-ibrahimovic / eduBOS5
  A compact, configurable RISC-V core
  ☆11Updated 3 months ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆23Updated 4 months ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆29Updated 6 years ago
• VHDL / PoC
  IP Core Library - Published and maintained by the Open Source VHDL Group
  ☆14Updated this week
• tmeissner / cryptocores
  cryptography ip-cores in vhdl / verilog
  ☆41Updated 4 years ago
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆48Updated last year
• efard / DSPHDL
  Digital Signal Processing and Well-Known Modulations on HDL
  ☆41Updated last month
• paulscherrerinstitute / psi_fix
  Fixed-point library with bittrue implementations in VHDL (for FPGA) and python (for simulation)
  ☆23Updated 11 months ago
• christoph-weiser / mpw6
  submission repository for efabless mpw6 shuttle
  ☆30Updated last year
• tmeissner / psl_with_ghdl
  Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)
  ☆66Updated 4 months ago
• suoto / fpga_cores
  ☆32Updated 2 years ago
• tsfpga / tsfpga
  A flexible and scalable development platform for modern FPGA projects.
  ☆28Updated this week
• paulscherrerinstitute / psi_fpga_all
  Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.
  ☆36Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆23Updated last year
• BerkeleyLab / Bedrock
  LBNL RF controls support HDL libraries. Mirroring LBNL's internal Gitlab repository, which is CI enabled
  ☆60Updated last week
• PyFPGA / HDLconv
  HDL converter (between VHDL, SystemVerilog and/or Verilog), based on GHDL, Yosys, Synlig, and the plugins ghdl-yosys-plugin and yosys-sla…
  ☆26Updated 3 months ago
• Toroid-io / vcd2wavedrom
  Python script to transform a VCD file to wavedrom format
  ☆77Updated 2 years ago
• Xilinx / chipscopy
  ChipScoPy (ChipScope Python API) is an open source Python API to the various ChipScope services provided by the TCF-based (Target Communi…
  ☆55Updated 3 weeks ago
• MJoergen / formal
  Playing around with Formal Verification of Verilog and VHDL
  ☆58Updated 4 years ago
• bpadalino / vhdl-format
  VHDL String Formatting Library
  ☆25Updated last year
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆62Updated 2 years ago
• nobodywasishere / VHDLproc
  VHDLproc is a VHDL preprocessor
  ☆24Updated 3 years ago
• alexforencich / cocotbext-uart
  UART models for cocotb
  ☆29Updated 2 years ago
• antmicro / topwrap
  A Python package for generating HDL wrappers and top modules for HDL sources
  ☆33Updated 2 weeks ago
• fransschreuder / xpm_vhdl
  A translation of the Xilinx XPM library to VHDL for simulation purposes
  ☆53Updated this week
• VUnit / tdd-intro
  Example of Test Driven Design with VUnit
  ☆14Updated 3 years ago