☆22Aug 25, 2016Updated 9 years ago
Alternatives and similar repositories for Zedboard-old
Users that are interested in Zedboard-old are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆15Sep 19, 2019Updated 6 years ago
- ☆18Jul 28, 2022Updated 3 years ago
- Architect's workbench☆10May 5, 2016Updated 10 years ago
- Source code for Zynq OLED controller☆16Oct 11, 2020Updated 5 years ago
- Hardware and script files related to dynamic partial reconfiguration☆11Mar 16, 2018Updated 8 years ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- SDSoC example projects☆13Mar 13, 2021Updated 5 years ago
- ☆14Mar 1, 2023Updated 3 years ago
- A toolkit for interactive visualization of signal and image processing on Jupyter Notebooks.☆11Mar 31, 2022Updated 4 years ago
- git clone from https://gnunet.org/svn/libmicrohttpd/☆13Feb 20, 2013Updated 13 years ago
- VCD Parser for Node.js☆11Jan 7, 2023Updated 3 years ago
- Chisel Examples for the iCESugar FPGA Board☆12May 4, 2021Updated 5 years ago
- Doppler effect on WaveForms☆17Sep 1, 2025Updated 9 months ago
- IPXACT packaging utilities for Chisel 3.x using Xilinx Vivado Design Suite.☆12Dec 5, 2018Updated 7 years ago
- Simple Memory Allocation Simulator. (Python)☆13May 7, 2023Updated 3 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Linux-kernel related code (patch form mark1/logibone support, kernel modules for communication, etc), can link to supported repositories☆23Apr 12, 2017Updated 9 years ago
- ☆17Sep 6, 2017Updated 8 years ago
- download from opencores.org☆16May 4, 2018Updated 8 years ago
- ☆25Apr 9, 2026Updated 2 months ago
- Auction Algorithms in C++☆14Mar 2, 2017Updated 9 years ago
- DLB (Deep Learning Blocks) as a part of DPU (Deep Learning Processing Unit) is a collection of synthesizable Verilog modules for deep lea…☆23Aug 13, 2025Updated 10 months ago
- stun server and client written in python, seems created by Franc Telecom RND☆19Apr 7, 2012Updated 14 years ago
- Express DLA implementation for FPGA, revised based on NVDLA.☆12Oct 17, 2019Updated 6 years ago
- Different version of the SMA-Q2 smartwatch replacement board☆18Feb 24, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- C++ program to simulate various cpu scheduling algorithms☆14Jun 30, 2024Updated last year
- Integrating Event-based Dynamic Vision Sensors with Sparse Hyperdimensional Computing☆12Jul 9, 2020Updated 5 years ago
- Symbolic differentation of algebraic expressions with Python and Tcl interfaces.☆19Oct 12, 2025Updated 8 months ago
- A reactor runtime written in C☆20Updated this week
- Try Lingua Franca now!☆21Updated this week
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆100May 24, 2022Updated 4 years ago
- Converting systemverilog to verilog.☆10Feb 15, 2018Updated 8 years ago
- A plugin for Hurricane VR that enables testing of VR gameplay using the mouse and keyboard, making it ideal for multiplayer development.☆17Jun 5, 2025Updated last year
- LIB:Library for loading and saving Cypress FX2LP firmware☆26Jan 16, 2021Updated 5 years ago
- Bare Metal GPUs on DigitalOcean Gradient AI • AdPurpose-built for serious AI teams training foundational models, running large-scale inference, and pushing the boundaries of what's possible.
- Used for hardware trojan detection（Based on Trust_Hub）☆10Jul 30, 2019Updated 6 years ago
- Setting up and updating to Hakchi2ce is now easy as 1, 2, 3!☆10Mar 23, 2018Updated 8 years ago
- ☆15Sep 14, 2020Updated 5 years ago
- The interactive demo of the interpretation of the anomaly detection with Triadic Motif Fields.☆14Apr 11, 2021Updated 5 years ago
- RISCV MYTH 4 stage pipelined core designed using TL-Verilog and supports RV32I base integer instruction set☆15Jan 14, 2021Updated 5 years ago
- 2 boards designed in Altium Designer 14, with digital meters☆16Jan 23, 2018Updated 8 years ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Jan 15, 2026Updated 4 months ago